View KE5B256B1CFP_8289862.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ver. 1.2.1 address processor 64k-bit ? 3-port type ke5b256b1
address processor ke5b256b1 table of contents 1. features 1.1 introduction 1.2 functional overview 1.3 specifications 1.4 register names 2. block diagram 3. pin assignment and pin descriptions 3.1 pin assignment 3.2 pin descriptions 4. port and operation mode overview 4.1 port overview 4.2 arbitration 4.3 operation modes overview 4.4 external arbitration 5. cam table 5.1 entry and segment 5.2 table configuration 5.3 read/write segment data 5.4 search and cam table 6. input port 6.1 input port configuration 6.2 ip sequence configuration 6.3 selection of channel and start sequence num- ber 6.4 ip sequence operation 6.5 hha automatic output 7. output port 7.1 op sequence configuration 7.2 selection of channel and start sequence num- ber 7.3 op sequence operation 8. cpu port 8.1 access to registers 8.2 basic operation through cpu port 8.3 search operation through cpu port 8.4 search result output from cpu port 8.5 hha/hea register operation 8.6 automatic increment function 8.7 table maintenance 9. cascading 9.1 device id registration 9.2 priority 9.3 cascade connection 9.4 input port in a cascade system 9.5 output port in a cascade system 9.6 cpu port in a cascade system 9.7 ac characteristics in a cascade system 9.8 single device operation 10. initialization 11. examples 12. command descriptions 12.1 command functions 12.2 conditions for executing commands 13. register descriptions 13.1 overview 13.2 register addresses 13.3 register bit maps 13.4 conditions for accessing registers 14. electrical characteristics 14.1 absolute maximum ratings 14.2 operating range 14.3 dc characteristics 14.4 ac characteristics 15. package outline
1-1 address processor ke5b256b1 1. features 1.1 introduction ke5b256b1 is a 256k-bit cam (content addressable memory) device with a new architecture. the main func- tion of the lsi is fast searching of data on the search data table stored in cam. user can define the row/column table size flexibility. the width of one entry in the search data table can be selected from 32 bits to 256 bits, in increments of 32 bits (1 segment). user can define the area to be searched in an entry freely in terms of the position and bit width. the search operation is executed for each segment, and the cycle time is 80ns with the fast operation charac- teristic of cams. ke5b256b1 provides 3 ports, an input port, output port and cpu port. these ports are designed to have the most appropriate functionality. the input port, which is only used for inputting the key data, provides the programmable input data formatter and programmable sequencer. these capabilities enable the formatting of the incoming key data and flexible search operation with any table column as a pre-determined se- quence by writing into the input port. therefore, user can execute complex search operations quickly. the search results can be output by flag pin and by register reading from the output port or the cpu port. the output port is only used for outputting the search re- sults. like the input port, it has a programmable se- quencer. the output port can output search results auto- matically according to a pre-determined sequence by read- ing from the output port. the cpu port is used for the definition of the search table, the table configuration/maintenance and the configuration of the input port and the output port . the cpu port has registers and commands by which user can realize func- tions easily. the registers can be accessed with direct ad- dressing, and there are various effect commands for table maintenance. the input/output data bus is 16 bits in width. an endian function is supported to make it easy to access the search table data of 32 bits. the upper 16 bits or the lower 16 bits of the segment can be read/written with the same address using the endian function. multiple devices can be easily cascade-connected in order to increase the number of entries in the cam table without external logic. the extended cam realized by cascade connection can be treated as if it were one continuous table in one device, because priority control is done internally between devices. however, the number of segments forming one entry in the search data table must be the same in all devices (even if the devices are not cascade connected). this device must arbitrate between ports to protect against data destruction caused by simultaneous access from plu- ral ports. user can select two methods of arbitration. one is an internal arbitration mode which restricts the device to internal operation by port-dependent modes (cpu mode, ip mode, op mode, iop mode). in this case, the device determines whether the device receives operations from every port or not. the other is external arbitration. in this case, simultaneous access from every port is not permitted. however, user can decrease the execution cycles, because instead of external arbitration, mode restriction is not ap- plied. user can select either method according to the re- quired applications.
1-2 address processor ke5b256b1 1.2 functional overview the ke5b256b1 (address processor: ap) provides the best solution to the fast and complex "address filtering" requirements of today's internetworking equipment with the following outstanding functions. (1) flexible search data table definition answering to vari- ous protocols. ? the entry size is configurable from 32 bits to 256 bits. ? the search operation of any width key data can be performed with data at any position in the table. ? all the cam area can be accessed as ram. (2) 3-port architecture ? optimized functionality for each port provides fast data processing. (3) programmable input data formatting and search se- quence ? the input data width can be selected as 32, 16, or 8 bits. ? definition of data input and search start position. ? masking by bit is possible. ? search window set by byte unit. ? maximum 8 step search sequence definition to any column of the table. (4) programmable output sequence ? output sequence definition of any search result. ? output sequence definition of any column of the hit entry. (5) multi-channel sequence ? a maximum of 16 kinds of ip sequences and op sequences can be defined by indicating the channel/ number of the start sequence. (6) cascading ? no additional logic is required. ? a cascaded table acts as one integral search data. (7) commands ? useful commands for the search table mainte- nance 1.3 specifications cam core ca p acit y 256 kbits access to table entry random access to all data (ram, cam s ubs titution) configuration configurable to control the entry width from 32 bits to 256 bits (entry size) in units of 32 bits ? 32 bits x 8,192 entries ? 64 bits x 4,096 entries ? 96 bits x 2,728 entries ? 128 bits x 2,048 entries ? 160 bits x 1,636 entries ? 192 bits x 1,364 entries ? 224 bits x 1,168 entries ? 256 bits x 1,024 entries cascadin g u p to 32 devices ( adds tabl e de p th ) search operation ? via cpu port ? via input port (automatic) ? mas k i ng by bi t ? search operation by table segment (32 bits) ? and search for more than 32 bits of data ? hit accumulation using access bit result output ? via cpu port ? via output port (automatic) ? hit result pin (ho_) ? intermediate search result pins (sh0_, sh1_) ?hit ? hit address ? entry data of hit address ? ke y data use d in se arch ope ration
1-3 address processor ke5b256b1 specifications (cont'd) ports in p ut port in p u t data bl oc k wi dth i s s e l e c tabl e ( 32 , 16 , or 8 bits ) ( ke y data i n p ut ) multi-channel: ip s e q uence of 2 channels ( a/b ) c an be de fi ne d. number of s tart s e q uence can be selected. in p ut port se q uence maxi mum 8 -s te p in p ut s e q uence confi g uration and data ( ip s e q uence ) formattin g functions. cut throu g h: an y block s electable amon g 6 4 blocks in data s tream data accumulation : most recent 64 bits can be tem p oraril y stored ( accumulation buffer & sub-accumulation buffer ) search window set: ke y data s electable with 3 2-bit width amon g 6 4 bits of accumulated data startin g from n ( n=0-3 , n b y te shift ) b y te mas k o p eration b y bi t an y se g ment can be searched in an y order. out p ut port 32 bits ( search result out p ut ) multi-channel op s e q uence of 2 channels ( a/b ) c an be de fi ne d. number of s tart s e q uence can be selected. out p ut port se q uence maxi mum 8 -s te p out p ut s e q uence confi g uration ( op se q uence ) search ke y data: ke y data after data formattin g used in the ip se q uence ( cmp0 - cmp7 re g ister ) hit s tatus : hit , multi-hit , used channel ( hs tat re g ister ) hit addres s : hit entr y address with the hi g hest p riorit y ( hha r e g ister ) contents of hit addres s ( memhha r e g ister ) * hit s tatus can be out p ut in combination with other search results cpu port 16-bit data , 8 -bi t addr e s s command execution re g ister read/write se q uence s q rs t_ ( pin ) reset ss q rs t command ( from cpu port ) search result ho_: results of each search o p eration out p ut p ins sh0_ , sh1_: intermediate search results of s p ecified ste p in the ip se q uence c y cle time 80ns i/f lvttl com p atible su pp l y vo l t a g e 3.3v 0.3v packa g e144- p in p q fp technolo gy 0.5 m cmos
1-4 address processor ke5b256b1 1.4 register names register names are described by the following abbreviations. abbreviations of registers abbreviation register name com register command register cntl register control register devid register device id register devstat register device status register devsel register device select register ar register address register memar register memory_ar register memhha register memory_hha register memhea register memory_hea register cpuhs register cpu hha/hea segment register memar_at register memory_ar attribute register memhha_at register memory_hha attribute register memhea_at register memory_hea attribute register shasgn register sequence hit flag assignment register hhasgn register hha automatic output assignment register cut register cut register ss register search start register cs register channel sequence register mask register mask register aoc register automatic output control register aosc register automatic output sub control register cpuinp register cpu input data register cpumask register cpu mask register cpusrs register cpu search segment register cpuinp2 register cpu input data 2 register cpumask2 register cpu mask 2 register cpusrs2 register cpu search segment 2 register hstat register hit status register estat register empty status register hha register highest hit address register hea register highest empty address register sh register sequence hit result register cmp register comparand register
2-1 address processor ke5b256b1 fig. 2-1 block diagram 2. block diagram od<31:0> input port (8, 16, 32 bits) wr id<31:0> data formatter input port sequencer ipch isnm<2:0> sqrst_ 32 bits mask 0 - 7 comparison logic cam array 8,192 words 32bits decoder empty bit hit flag access bit priority encoder 32 bits output port sequencer opch opns a ch b ch a ch b ch 32 bits output port oe_ rd_ 32 bits command control status memory r/w configuration cpu search table status 16 bits cpu port 16 bits ce_ r/w_ rst_ sp/tp_ dat<15:0> add<7:0> 8 bits flag logic fli_ flo_ pi_ po_ hi_ ho_ sh0_ sh1_ ipbusy_/opact_ opbusy_/ipact_ 16 bits
3-1 address processor ke5b256b1 fig. 3.1.1 pin assignment KE5B256B1CFP (144-pin pqfp type) 3. pin assignment and pin descriptions 3.1 pin assignment 36 37 1 144 109 73 72 108 index KE5B256B1CFP qfp144 ? ? ? ? ? ? ? ? ? ? ???? ????
3-2 address processor ke5b256b1 table 3.1 pin assignment pin no. signal name i/o type pin no. signal name i/o type 1 vdd - 41 id<22> in 2 od<2> out 42 id<23> in 3 od<1> out 43 id<24> in 4 od<0> out 44 id<25> in 5 oe_ in 45 id<26> in 6 po_ out 46 id<27> in 7 pi_ in 47 id<28> in 8 sh1_ out 48 id<29> in 9 sh0_ out 49 id<30> in 10 ho_ out 50 id<31> in 11 hi_ in 51 ipbusy_/opact_ out 12 flo_ out 52 opbusy_/ipact_ out 13 vdd - 53 w r in 14 id<0> in 54 gnd - 15 id<1> in 55 gnd - 16 id<2> in 56 gnd - 17 gnd - 57 sqrst_ in 18 gnd - 58 rst_ in 19 gnd - 59 rd_ in 20 id<3> in 60 add<0> in 21 id<4> in 61 add<1> in 22 id<5> in 62 add<2> in 23 id<6> in 63 add<3> in 24 id<7> in 64 add<4> in 25 id<8> in 65 add<5> in 26 id<9> in 66 add<6> in 27 id<10> in 67 add<7> in 28 id<11> in 68 gnd - 29 id<12> in 69 r/w _ in 30 id<13> in 70 ce_ in 31 id<14> in 71 nc open* 1 32 id<15> in 72 vdd - 33 id<16> in 73 vdd - 34 id<17> in 74 dat<0> io 35 id<18> in 75 dat<1> io 36 vdd - 76 dat<2> io 37 vdd - 77 dat<3> io 38 id<19> in 78 dat<4> io 39 id<20> in 79 dat<5> io 40 id<21> in 80 gnd -
3-3 address processor ke5b256b1 *1 nc pins should be open. (do not connect.) table 3.1 pin assignment (cont'd) pin no. signal name i/o type pin no. signal name i/o type 81 vdd - 121 od<19> out 82 dat<6> io 122 od<18> out 83 dat<7> io 123 od<17> out 84 dat<8> io 124 od<16> out 85 dat<9> io 125 gnd - 86 dat<10> io 126 gnd - 87 dat<11> io 127 gnd - 88 dat<12> io 128 od<15> out 89 dat<13> io 129 od<14> out 90 gnd - 130 od<13> out 91 gnd - 131 od<12> out 92 gnd - 132 vdd - 93 dat<14> io 133 od<11> out 94 dat<15> io 134 od<10> out 95 isnm<0> in 135 od<9> out 96 isnm<1> in 136 od<8> out 97 isnm<2> in 137 gnd - 98 opns in 138 od<7> out 99 ipch in 139 od<6> out 100 opch in 140 od<5> out 101 gnd - 141 od<4> out 102 od<31> out 142 od<3> out 103 od<30> out 143 nc open* 1 104 od<29> out 144 vdd - 105 sp/tp_ in 106 nc open*1 107 fli_ in 108 vdd - 109 vdd - 110 od<28> out 111 od<27> out 112 od<26> out 113 od<25> out 114 od<24> out 115 gnd - 116 od<23> out 117 od<22> out 118 od<21> out 119 od<20> out 120 vdd -
3-4 address processor ke5b256b1 function dat<15:0> add<7:0> ce_ r/w_ rst_ id<31:0> 3.2 pin descriptions pin name attribute cpu port data bus input / output tri-state lvttl cpu port address bus input lvttl device enable input lvttl read/write input lvttl hardware reset input lvttl input port data bus input lvttl dat<15:0> is a 16-bit, bidirectional data bus used to con- vey data, commands, and status to and from the address processor (ap). the direction is controlled by the state of r/w_. dat<15:0> is enabled by a low level of ce_. add<7:0> is an 8-bit address bus used to select registers. ce_ is used for access from the cpu port. r/w_, add, dat inputs are latched on the falling edge of ce_. r/w_ low selects a write cycle. r/w_ high selects a read cycle. the state of r/w_ is registered on the falling edge of ce_. rst_ is a hardware reset signal. a low pulse of rst_ ini- tializes the ap. the minimum low hold time is 40ns. id<31:0> is a 32-bit data bus used to convey search data to the ap through the input port. the id bus width can also be configured to 8 bits (id<7:0>) or 16 bits (id<15:0>).
3-5 address processor ke5b256b1 function pin name attribute input port write pulse input lvttl port number select input lvttl input/output port sequence pointer reset input lvttl output port data bus output lvttl output port read pulse input lvttl output port outpt enable input lvttl wr sp/tp_ sqrst_ od<31:0> rd_ oe_ wr controls the search operation through the input port. users can select the polarity of wr. according to the cut through configuration, data on the id bus is transferred on the falling edge (negative pulse) or the rising edge (positive pulse) of wr. sp/tp_ controls the mode restriction for register access and command execution. when the sp/tp_ is pulled down, the use of independent triple ports and restricts some operations in the cpu mode. when the sp/tp_ is pulled up, the use of like a single port and reduces the re- striction. sqrst_ is a sequence pointer reset signal for the input port and output port. a low pulse of sqrst_ initializes the input port sequence pointer and output port sequence pointer. low hold time requires more than 40ns. od<31:0> is a 32-bit data bus used to output the results of a search operation. rd_ controls the read access through the output port. the output port read cycle starts on the falling edge of rd_. the od bus outputs the results of the search operation ac- cording to the output sequence configuration. oe_ enables the od output. when oe_ is low, the od output drivers are enabled. when oe_ is high, od bus im- pedance becomes high.
3-6 address processor ke5b256b1 function pin name attribute input port busy/ output port active output lvttl output port busy/ input port active output lvttl hit flag output output lvttl hit flag input input lvttl ipbusy_/opact_ opbusy_/ipact_ ho_ hi_ ipbusy_/opact_ is used to monitor the status of port operation. when the sp/tp_ pin is pulled down, this pin becomes a busy signal for the input port. this pin is low during the output port read cycle or cpu mode. on the other hand, when the sp/tp_ pin is pulled up, this pin be- comes an active signal for the output port. this pin is low during the output port read cycle. opbusy_/ipact_ is used to monitor the status of port operation. when the sp/tp_ pin is pulled down, this pin becomes a busy signal of the output port. this pin is low during the input port read cycle or cpu mode. on the other hand, when the sp/tp_ pin is pulled up, this pin be- comes an active signal for the input port. this pin is low during the input port write cycle. ho_ is used to output search results. this pin is low when even one hit occurs in the search operation. this pin is high when no entry is hit. in a cascaded system, the hit signal of the cascade configuration appear the ho_ output of the lowest priority device (last device). hi_ is used in the cascaded system. hi_ input is connected to the ho_ output of the adjacent higher priority device. this connection propagates hit information from a high priority device to a lower priority device. the hi_ pin of the highest priority device should be pulled up in a cas- caded system, and in a single system, the hi_ pin of the device should be pulled up.
3-7 address processor ke5b256b1 function pin name attribute sh0_, sh1_ po_ pi_ flo_ sequence hit flag output open drain priority output output lvttl priority input input lvttl full flag output output lvttl sh0_ and sh1_ are used to output the intermediate search results in a search sequence from the input port. when there are search results of a specified sequence number, this pin is low. on the other hand, when there is no hit, this pin has high impedance. sh0_ and sh1_ are programmably se- lected and output intermediate search results. po_ is used to propagate priority information of the device and to output multi-hit information. in a cascaded system, this pin propagates priority information (devid priority) of cascaded system to the lower priority device. this pin is also used as a multi-hit status flag. when this pin is low, multi-hit occurs. in a cascaded system, the po_ pin of the lowest priority device (last device) outputs sys- tem multi-hit information. pi_ is used in a cascaded system. the pi_ input is con- nected to the po_ output of the adjacent higher priority de- vice. this connection propagates devid priority from a high priority device to a lower priority device. multi-hit in- formation is also propagated by this connection. the pi_ pin of the highest priority device should be pulled up in a cascaded system, and in a single system, the pi_ pin of the device should be pulled up. flo_ is used to output search results. this pin is low when all entries in the cam are filled with effective entries (full status) and there is no entry for new registration. in a cascaded system, the full signal of the cascade configu- ration appears at the flo_ output of the lowest priority de- vice (last device).
3-8 address processor ke5b256b1 function pin name attribute fli_ ipch isnm<2:0> opch full flag input input lvttl input port channel input lvttl input port start sequence number select input lvttl output port channel input lvttl fli_ is used in a cascaded system. the fli_ input is con- nected to the flo_ output of the adjacent higher priority device. this connection propagates full/empty information from a high priority device to a lower priority device. the fli_ pin of the highest priority device should be pulled up in a cascaded system, and in a single system, the hi_ pin of the device should be pulled up. ipch determines the input port active channel when hard- ware channel selection is defined in the cntl register. the state of ipch is registered on the falling edge of the sqrst_ pulse or ce_ pulse of the ssqrst command. ipch low selects channel "a" and high selects channel "b." isnm<2:0> is used to indicate the start search sequence number. when a hardware channel selection is defined in the cntl register, this 3-bit field indicates the start ip sequence number directly. signals on this fields are latched on the falling edge of the sqrst_ pulse or ce_ pulse of the ssqrst command. opch determines the output port active channel when hardware channel selection is defined in the cntl regis- ter. the state of opch is registered on the falling edge of the sqrst_ pulse or ce_ pulse of the ssqrst com- mand. ipch low selects channel "a" and high selects channel "b."
3-9 address processor ke5b256b1 function pin name attribute output port start sequence number selection input lvttl supply supply opns vdd gnd opns is used to indicate the start output sequence number. this pin determines whether the op start sequence number is "0" or a number indicated in the cntl register. a signal on the opns pin is latched on the falling edge of sqrst_ pulse or ce_ pulse of the ssqrst command. when this pin is low, the sequence number "0" is selected. on the other hand, when this pin is high, the sequence number pointed in the cntl register is selected. power supply: 3.3v 0.3v ground
4-1 address processor ke5b256b1 4. port and operation mode overview 4.1 port overview ke5b256b1 has an input port, which is only used to input search key data, an output port, which is only used to out- put search results, and a cpu port, which is used to control the device, for table configuration, and for table mainte- nance. an overview of each port is presented below. input port the 32-bit input port receives data for search opera- tions. the port width is 32-bit in width, but it can be configured to 16 or 8 bits. when 16 or 8 bits are configured, 16 or 8 bits on the lsb side of id<31:0> are used, with 16 bits, id<15:0> is effective. with 8 bits, id<7:0> is effective. the data on the id<31:0> is input into the device by applying a writing pulse (wr pulse) to the wr pin. a pre-defined search sequence (ip sequence) then executes. the polarity of the wr pulse is program- mable, and can be configured by the user to a negative or positive pulse. the wr pulse cycle is called the input port cycle. a sequencer in the input port operates synchronously with the wr pulse. the sequence executes the following pro- cesses. (1) cut through only desired data blocks as search keys are picked up from among the input data stream applied from the input port. (2) data accumulation the data blocks picked up in the cut through process are stored in an accumulation buffer and a sub-accumulation buffer in the device. the total number of bits which can be stored in the accumulation buffer and sub-accumulation buffer is 64 bits. (3) search window setting a 32-bit data block is selected as the search key data from among the 64-bit data block stored in the above two buff- ers. the position of the window can be set by byte. (4) mask operation the 32 bits of search key data selected can be masked by bit. masked bits are not compared with the corresponding bits of the search key data. (5) selection of search segments a column position (segment) in the search data table to be searched is selected. (6) execution of search these sequencer operation (ip sequence) is programmable. each step of the search operation can be defined indepen- dently. two sets of the ip sequence can be defined (2-chan- nel architecture). each channel can contain a maximum of 8 steps. two kinds of sequences can execute by changing these channels. furthermore, user can use the sequencer dividing function. in this case, a maximum of 16 kinds in an ip sequence, which have various search mask definitions and search segment definitions, can be defined (multi-chan- nel). see chapter 6 for a detailed discussion of ip sequence definitions. output port the 32-bit output port provides search results. the data is output synchronously with an rd_ pulse on the od<31:0>. the cycle of the rd_ pulse is called the out- put port cycle. there are several search results output from the output port as listed below.
4-2 address processor ke5b256b1 ? hit status (hit, multi-hit, etc.) ? address of the hit entry ? stored data of the hit entry ? key data used in the ip sequence users can define which of the results are output and the numbers of which the results are output in the sequencer (op sequence). the op sequence is also constructed of two channels, and each channel can contain a maximum of 8 steps (as in the ip sequence). users can use the sequencer dividing func- tion and define multi-channel sequences. see chapter 7 for a detailed discussion of ip sequence definitions. cpu port the cpu port has a 16-bit data bus dat<15:0> inter- facing with the host processor. the address add<7:0> determines which register is accessed in the device. each operation through the cpu port is executed synchro- nously with a ce_ low pulse. the ce_ pulse cycle is called the cpu port cycle. an r/w_ signal determines whether a cycle is a reading cycle or a writing cycle. all operations using the cpu port are executed by reading or writing registers indicated by the address bus (add<7:0>). the processes executed by the cpu port are presented below. (1) setting of basic device operations this setting is executed by writing the cntl register. the contents of the setting are an endian function (see chapter 5) polarity of the wr pulse and a method of ip/op channel selection (see chapters 6, 7). a detailed discussion of the bit map of the cntl register is presented in section 13.3. (2) device id registration (only for cascaded systems) with a cascaded system, the device id must be registered. a detailed discussion of device id registration is presented in section 9.1. (3) cam table configuration the column size (entry width) and row size (entry number) of the cam table must be defined. this definition is called a table configuration. see chapter 5 for a detailed discussion. (4) ip/op sequence definition the search sequence of the input port (ip sequence) and the output sequence of the output port are defined. a method of input data formatting, mask operation, and the search segment can defined by setting the cut register, ss register, cs register, and mask register for the ip se- quence. see section 6.2 for a detailed discussion. a pointing the search required results (status, address, data) and output segment can defined by setting the aoc register and aosc register. a detailed discussion is pre- sented in section 7.1. (5) cam table creation and maintenance the creation and maintenance of the cam table are ex- ecuted by accessing data in the cam. this operation can be executed by both the former operation and also by using a maintenance command. see chapter 8 for a detailed discus- sion. (6) command execution commands can be executed by writing an op-code into the com register. some commands are prepared for mode change, device reset, ip/op sequence reset, and table main- tenance.
4-3 address processor ke5b256b1 (7) search operation a search operation may be also executed through the cpu port. however, automatic search operations cannot be defined in search operations through the cpu port, (as with the ip sequence). the key data, mask data, or search segment number should be set up in the cpuinp, cpumask, or cpusrs register prior to performing the srch command. a detailed discussion is presented in chapter 8. (8) search results the results of the search operation can be output via the cpu port by reading the registers (e.g. hstat, estat, hha, sh, and cmp) which store the hit status, hit address, and intermediate hit information of the ip se- quence. stored data of the hit entry can be output by read- ing the memhha register. for a detailed discussion, see chapter 8. in access to the cam table of above-mentioned operations (3, 5, 7, and part of 6, 8), simultaneous access through the input port and output port is not permitted to protect the cam table data against destruction. however, register ac- cess except for the cam table and execution commands with no relation to cam table manipulation can be ex- ecuted while the input port and output port are running, because is access will not cause cam table destruction. a detailed discussion of operations which are not permitted simultaneously is presented in table 4.3.1. 4.2 arbitration this device is not permitted to access through plural ports simultaneously to protect against the cam data destruc- tion. therefore, it is necessary to arbitrate operations through the three ports (cpu, input, output) using one of the two methods described below. (1) internal arbitration internal arbitration restricts access simultaneous to the de- vice through plural ports according to the operation mode. the operation modes in internal arbitration include the cpu mode, in which a host processor mainly operates , the ip mode, in which the ip sequence is executed, the op mode, in which the op sequence is executed, and the iop mode, which is a waiting mode for shifting to the ip or op mode. an tc sub-mode for table definition and a devid sub-mode for device id registration are also included. in internal arbitration, for example, in the cpu mode, the device is controlled so as not to execute operations through the input port (ip sequence) and the output port (op se- quence). therefore, a shift mode operation is necessary be- fore executing the required operations. (2) external arbitration external arbitration is a method that restricts access simul- taneous to the device through plural ports external to the device. for example, when access signals to each port are created by the same clock, accesses to each port can be exclusive. in this case, the command for shifting modes can be omitted using external arbitration. there is basically no mode concept in external arbitration. the only restrictions are on the operation modes that are related to the tc sub-mode for table definition and a devid sub-mode for device id registration. the sp/tp_ pin determines which arbitration method is se- lected. when the sp/tp_ pin is pulled down, the internal arbitration is selected. if pulled up, external arbitration is selected.
4-4 address processor ke5b256b1 4.3 operation modes overview as mentioned above, during internal arbitration, operation of the device is restricted by the operation mode. a detailed discussion of each mode is given below. cpu mode the cpu mode is used to access the device through the cpu port. in this mode, accesses through the input port and output port become invalid. transition to the cpu mode is executed by the device reset operation (applying a low pulse to the rst_ pin or issuing the srst command) or issuing the swcpup and swcpu_im commands. operation through the cpu port is basically in the cpu mode, but there are operations which can be executed in the other modes. in internal arbitration, operations related to the cam table can not be executed by shifting to the cpu mode. operations which can be performed only in the cpu mode are discussed below for the internal arbitration. ? writing the cntl register the cntl register is different from the cam core, but this register cannot be written in the only cpu mode because the basic definitions of the cntl register are important in- formation for accessing to the cam table. reading of the cntl register can be executed in the other modes. ? creating the cam table and maintenance commands for read/write data of the cam table can be executed to protect against data destruction due to simulta- neous access through the input port and the output port when only the cpu mode can be executed. ? reading the cmp register the cmp register can also be accessed to protect against data destruction due to simultaneous access through the in- put port and output port when only the cpu mode can be executed. when you execute the above operation, which can be ex- ecuted only in the cpu mode, be careful about mode shift- ing. a summary of the operations which are not permitted simultaneous access through the input port or output port is presented in table 4.3.1. devid sub-mode the devid sub-mode, which belongs to the cpu mode, is used to register a unique device id for every cascaded device. the following operations require to registration of a device id in the devid sub-mode. ? str_devid command ? read/write to the devid register ? nxt_pr command ? end_devid command do not use the devid sub-mode except in device id reg- istration. in the case of a single device, the devid sub- mode is not necessary to use because device id registra- tion is not necessary. see section 9.1 for a detailed discus- sion of device idregistration. tc sub-mode in the tc sub-mode, which belongs to the cpu mode, user defines how many segments (1 segment = 32 bits) the cam table has as one entry. this operation is called table con- figuration. in the tc sub-mode, only the following opera- tions which are necessary to configure the cam table are performed. ? str_tc command ? read/write ar register (pointing the cam address)
4-5 address processor ke5b256b1 table 4.3.1 prohibited operations in simultaneous access through input port and output port ? read/write memar register (read/write tc data) ? end_tc command these commands cannot be used except in table configura- tion. table configuration must be executed when user uses the device. a detailed discussion of table configuration is presented in section 5.2. iop mode the iop mode is the stand-by state for the ip mode or op mode. the device moves the iop mode from the cpu mode when an swiop command is executed. in this mode, the sequencer in the input port starts to operate automati- cally, and the mode of the device moves to the ip mode (note 1). when the defined ip sequence ends, the mode returns to the iop mode automatically. when an rd_ pulse is applied in the iop mode, the se- quence in the output port starts to operate and the mode of the device moves to the op mode. when the defined op sequence ends, the mode returns to the iop mode. in the iop mode, operations (e.g. accessing the cam table through the cpu port) which are permitted only in the cpu mode cannot be executed. when user wishes to ex- ecute these operation, it is necessary to change the cpu mode by issuing an swcpup command or swcpup_im command. ip mode the input port is active in the ip mode. when a wr pulse is applied to the input port in the iop mode, the mode of the device moves the ip mode and the search operation starts according to the defined sequence. the search opera- tion is executed synchronously with the wr pulse, and the operations content of operation register access to cam table memar register read/write memhha register read/write memhea register read/write memar_at register read memhha_at register read memhea_at register read command to cam table s rch command gen_hit command s rch2 command nxt_ he command prg_ al command gen_fl command prg_ nac command append command prg_ ac command append_ nhe command rst_ac command restore command prg_ nacwh command s tmp_ar command prg_ acwh command s tmp2_ ar command rs t_acwh command s tmp_hh command p r g_ hh c omman d s tmp 2 _ hh c omman d prg_ ar command s tmp_he command nxt_ hh command s tmp2_ he command secondary register access to cam table cntl register write cmp register read
4-6 address processor ke5b256b1 sequence is processed step by step. the ip sequence pointer increases with each step. when the pointer arrives at the step which is defined as the end of the sequence, the pointer stops and the mode returns to the iop mode auto- matically. however, when the mode returns to the iop mode, the ip sequence will not operate even when a wr pulse is input, because the sequence pointer is stopped. if user wishes to start the ip sequence again, it is necessary to initialize the stopped pointer. inputting an sqrst_ low pulse or issuing an ssqrst command initializes the pointer. in the ip mode, an output operation through the output port and the operations (e.g. accessing the cam table through the cpu port) which are permitted only in the cpu mode cannot be executed. when interrupt commands (swcpup, cwcpup_im, swcpup_sqe command) are executed before the end of the ip sequence, the device moves the cpu mode accord- ing to the timing of the command specification. a detailed discussion of interrupt commands through the cpu port is presented in a later section. op mode the output port is active in the op mode. when an rd_ pulse is applied to the output port in the iop mode, the mode of the device moves to the op mode and the output operation starts according to the defined sequence. the output operation is executed synchronously with the rd_ pulse and the sequence is processed step by step. the op sequence pointer with each step. when the pointer arrives at the step which is defined as the end of the sequence, the pointer stops and the mode returns to the iop mode auto- matically. when the mode returns to the iop mode, the op sequence will not operate when an rd_ pulse is input, be- cause the sequence pointer is stopped. users who wish to restart the op sequence should initialize the stopped pointer using the sequence pointer reset operation. in the op mode, the search operation through the input port and the operations (e.g. accessing the cam table through the cpu port) which are permitted only in the cpu mode cannot be executed. when the interrupt com- mands are executed before the end of the ip sequence, the device moves the cpu mode according to the timing of the command specification. (note 1) the sequence pointer reset operation with chang- ing to the iop operation is necessary to start the sequence.
4-7 address processor ke5b256b1 mode transition and command mode transition is shown in fig. 4.3.1 when the sp/tp_ pin is pulled down (in internal arbitration). the mode transition is controlled by the wr, rd_ pulses or command. a de- tailed discussion is presented below. cpu mode => iop mode the transition of the iop mode from the cpu mode is ex- ecuted basically by executing the swiop command. some of the commands which are executed in the cpu mode have the swiop command function. after these com- mands execute, the device can return to the iop mode im- mediately. this function is called the automatic swiop function. users can determine whether to use the automatic swiop function or not by setting the cpuhs register. this function omits issuing of the swiop command, and can make processes more efficient. the following 8 com- mands have the automatic swiop function. see chapters 8 and 12 for a detailed discussion of each command. ? append commands append command append_nhe command ? stamp commands stmp_ar command stmp_hh command stmp_he command stmp2_ar command stmp2_hh command stmp2_he command iop mode => ip mode the transition to the ip mode from the iop mode is ex- ecuted by inputting a wr pulse. however, when the se- quence pointer stops, the wr pulse is not received and the mode transition is not executed. if user wishes to move the ip mode (starting ip sequence), the sequence pointer reset operation must be executed beforehand. the sequence pointer reset operation can be executed before the swiop command. ip mode => iop mode when a predefined ip sequence ends, the mode of the de- vice returns to the iop mode. when the sequence pointer reset operation is executed in the ip mode, the mode re- turns to the iop mode without waiting for the end of the ip sequence. users who wish to have the mode return to the iop mode in the middle of an ip sequence should use, the sequence pointer reset operation. (see chapter 14.) iop mode => op mode the transition to the op mode from the iop mode is ex- ecuted by inputting an rd_ pulse. however, when the se- quence pointer stops, the rd_ pulse is not received and the mode transition is not executed. if user wishes to move the op mode (starting op sequence), the sequence pointer re- set operation must be executed beforehand. the sequence pointer reset operation for the op sequence is not neces- sary if the sequence pointer reset operation is executed be- fore the ip sequence which corresponds to the op se- quence, because the sequence pointer reset operation ini- tializes both the ip sequence pointer and the op sequence pointer. op mode => iop mode when a predefined op sequence ends, the mode returns to the iop mode. when the sequence pointer reset operation is executed in the op mode, the mode returns to the iop mode without waiting for the end of the op sequence. us- ers who wish to have the mode return to the iop mode in middle of an op sequence should use, the sequence pointer reset operation. (see chapter 14.)
4-8 address processor ke5b256b1 * device reset rst_pulse or srst command ** sequence pointer reset sqrst_pulse or ssqrst command power on *sp/tp_ p ull down device reset devid sub-mode cpu mode iop mode ip mode op mode rd_pulse wr pulse normal o p eration state tc sub-mode str_devid command end_devid command str_tc command end_tc command sequence pointer reset ** end of op sequence sequence pointer reset ** end of ip sequence end of op sequence after swcpup, swcpup_sqe command execution end of op cycle after swcpup_im command execution swiop command stamp, append command with automatic swiop command end of ip sequence after swcpup, swcpup_sqe command execution end of ip cycle after swcpup_im command execution swcpup command swcpup_im command fig. 4.3.1 state diagram in internal arbitration table 4.3.2 ipbusy_/opact_, opbusy_/ipact_ in internal arbitration ipbusy_/opact_ opbusy_/ipact_ cpu mode l l (i n c l udi n g devid s u b-mode an d tc s u b-mode ) ip mode h l op mode l h iop mode h h
4-9 address processor ke5b256b1 iop mode => cpu mode the swcpup command or swcpup_im command is is- sued to move the mode to the cpu mode from the iop mode. ip mode/op mode => cpu mode (cpu interrupt) when the cpu interrupt commands (swcoup, swcpu_im, swcpup_sqe) are issued, user can move the mode to the cpu mode from the ip mode/op mode without using the iop mode. a detailed discussion of cpu interrupt commands is presented below. ? swcpup command when a swcpup command is issued during an ip se- quence/op sequence, the cpu interrupt is reserved and the device moves to the cpu mode without passing through the iop mode after the end of the sequence being executed. when a swcpup command is issued in the iop mode, the device moves to the cpu mode immediately. ? swcpup_sqe command a swcpup_sqe command also moves the mode to the cpu mode after the end of the ip sequence/op sequence. however, when the command is issued in the iop mode, the interrupt is only reserved and the device does not move to the cpu mode immediately. this point is different from the swcpup command. in this case, the transition to the cpu mode is also executed after the end of the ip se- quence/op sequence. ? swcpup_im command when an swcpup_im command is issued during an ip sequence/op sequence, the cpu interrupt is reserved im- mediately and the device moves to the cpu mode without waiting for the end of sequence being executed. the input port cycle/output port cycle, which is executed when an swcpup_im command is issued, continues to operate and the device moves to the cpu mode at the end of the cycle. when an swcpup_im command is issued in the iop mode, the device moves to the cpu mode immedi- ately. the ip sequencer/op sequencer detects the issuance of the above-mentioned cpu interrupt commands at the edge of the wr/rd_ pulse. (see chapter 14, cpu interrupt in the ip mode/op mode.) when the timing shown in chapter 14 is not observed, the command is not detected until the next edge of the wr/rd pulse, and the transition to the cpu mode is executed late. the transition to the cpu mode can be confirmed by the devstat register or the ipbusy_/ opact_ pin and opbusy_/ipact_ pin. if there is no wr/rd_ pulse for some reason, the interrupt command is not detected and the transition to the cpu mode is not executed. in this case, the swcpup command can move the device to the cpu mode after the ip/op se- quence is stopped by a sequence pointer reset operation. cpu mode <=> devid sub-mode normal transition to the devid sub-mode from the cpu mode is executed by issuing an str_devid command. the end_devid command is issued to return to the cpu mode after device id registration. cpu mode <=> tc sub-mode normal transition to the tc sub-mode from the cpu mode is executed by issuing an str_tc command. the end_tc command is issued to return to the cpu mode after table configuration. users can confirm the mode of the device by reading the devstat register or the ipbusy_/opact_ pin and opbusy_/ipact_ pin. the ipbusy_/opact_ and opbusy_/ipact_ pins be-
4-10 address processor ke5b256b1 come busy signals in internal arbitration, as shown in table 4.3.2. both the ipbusy_/opact_ and opbusy_/ipact_ pins become low and indicate "busy" to the input port/ output port in the cpu mode (including the devid sub- mode and tc sub-mode). the opbusy_/ipact_ pin becomes low to prohibit op- eration through the output port and indicates "busy" of the output port. the ipbusy_/opact_ pin becomes low to prohibit operation through the input port and indicates "busy" of the input port. the ipbusy_/opact_ and the opbusy_/ipact_ pins become high to indicate a ready status to the ip sequence or the op sequence in the iop mode. the cpf bit of the devstat register is a flag which indi- cates that the mode is the cpu mode in internal arbitration. the ipf bit of the devstat register is a flag which indi- cates that the mode is the ip mode in the internal arbitra- tion. the opf bit of the devstat register is a flag which indicates that the mode is the op mode in the internal arbi- tration. see chapter 13 for a detailed discussion of the bit map of the devstat register. examples of typical use in the internal arbitration are pre- sented below. when the device reset operation by an rst_ signal (or the srst command) is executed, the device moves to the cpu mode automatically. after power on, a device reset opera- tion by a low pulse of the rst_ signal must be executed. the device reset operation initializes many registers. the initialized values are shown in chapter 13. registers for the ip sequence/op sequence have pre-determined initial values. register the device id in every device by moving the devid sub-mode after the device reset operation in a cas- caded system. after device id registration, the transition back to the cpu mode is executed by an end_devid command. see chapter 9 for a detailed discussion of de- vice id registration. in the case of a single device, device id registration is not necessary. first, execute a designation of the device operation by setting the cntl register in the cpu mode after the device reset operation (device id registration in a cascaded sys- tem). (a detailed discussion of the cntl register is pre- sented in chapter 13.) second, execute a table configuration by moving to the tc sub-mode. when the table configuration of all cam words ends, the transition back to the cpu mode is executed by the end_tc command. third, execute the create table operation (writing table data). see chapter 8 and 12 for a detailed discussion of the command set for accessing and maintenance of the cam table. execute ip sequence/op sequence definition by setting the cut register, ss register, cs register, mask register, aoc register, and aosc register. a detailed discussion is presented in section 6.2 and 7.1. after all the above processes have been executed in the cpu mode, the device can be activated. when the swiop command is issued at this time, the cpu mode ends and the device moves to the iop mode. when the wr pulse is input after a sequence pointer reset operation in the iop mode, the device moves to the ip mode and executes the ip sequence according to the defini- tion. when the ip sequence ends, the mode moves to the iop mode automatically. at this time the device moves to the op mode when an rd_ pulse is input, and user can fetch the results of the ip sequence using the op sequence. when the op sequence
4-11 address processor ke5b256b1 ends, the device returns to the iop mode. when modifying/appending data in the cam table after an ip sequence or op sequence, issue the above cpu inter- rupt command and move the device to the cpu mode. af- ter modifying/appending data in the cam table, the device is moved to the iop mode by a swiop command. if a sequence pointer reset operation is not executed, the device is not moved to the waiting state for the transition to the ip mode. the sequence pointer reset operation can be also executed in the cpu mode or after the transition to the iop mode. 4.4 external arbitration as described in section 4.2, external arbitration is a method outside the device which prohibits simultaneous access to the device through plural ports. for example, when accessing signals to plural ports (wr, rd_, and ce_) are given from the same system clock and only one becomes active, a sufficient interval for all signals can be secured because only one signal always accesses the device. when the interval for accessing from every port is guaranteed to obtain a determined time width outside the device, external arbitration can be defined. when external arbitration is defined, the mode restriction for all operations disappears and the issuing of commands (swiop, swcpup, swcpu_im, swcpup_sqe) for mode transition is not necessary. therefore, process cycles can be decreased when much accessing of the cam table through the input port and output port and modification of the cam table through the cpu port are required. how- ever, the tc sub-mode for table configuration and the devid sub-mode for device id registration is neces- sary to move the device to the sub-mode. a comparison with mode transition in internal arbitration is shown in fig. 4.4.1. the external arbitration operations are described below. the device reset operation is also necessary in external ar- bitration after power on. the device should then be moved to the devid sub-mode using a str_devid command in cascaded systems and the device id should be registered. after device id registration, execute an end_devid command. after setting the cntl register, move the device to the tc sub-mode using a str_tc command and execute table configuration. after table configuration, exit the device from the tc sub-mode using an end_tc command. after writing the table data or the ip/op sequence configu- ration, the ip sequence or op sequence can start without an swiop command if the sequence pointer reset operation is executed. in modification/appending of the table data ( entry) after the end of the ip sequence or op sequence, the mode transition using an cpu interrupt command is not necessary. therefore swiop, swcpup, swcpup_im, and swcpup_sqe commands are completely unneces- sary. however, the user should control the device from the outside to maintain the timing specifications between the wr and the rd_, wr and ce_, rd_ and ce_ signals. if the operations through the cpu port by the ce_ are not related to the cam table (other than in table 4.3.1), there is no timing restriction between the ce_ pulse and wr, rd_ pulses.
4-12 address processor ke5b256b1 if user observes the above-mentioned timing restrictions among signals, mode transition is not necessary except for the transition to the tc sub-mode for table configuration and transition to the devid mode for device id registra- tion. the op sequence can start during the ip sequence (before finishing the ip sequence completely), and the ip sequence can continue to execute again. that is, both the ip sequence and op sequence can run simultaneously. how- ever, adequate care should be used in sequence configura- tion. in external arbitration, there is no mode concept. the cpf bit of the devstat register is set to "1" after a device reset operation and indicates the same status as in the cpu mode. however, this bit does not change there after. the ipf and the opf bits of the devstat register are initial- ized to "0," and these bits become "1" when the ip se- quence/op sequence is running. the opbusy_/ipact_ pin is not a busy signal for the output port, but becomes a port active signal which indi- cates whether the input sequence is running or not. the ipbusy_/opact_ pin is not a busy signal for the input port, but becomes a port active signal which indicates whether the output sequence is running. the above discussion is summarized in table 4.4.1. after the sequence pointer reset operation, both the opbusy_/ ipact and the ipbusy_/opact_ pins become high, and indicate that both the ip sequence and the op sequence do not start. when the ip sequence starts due to a wr pulse, the opbusy_/ipact_ pin becomes low, and indicates that the ip sequence is running. the opbusy_/ipact_ pin becomes high when the sequence ends. on the other hand, when the op sequence starts due to a rd_ pulse, the ipbusy_/opact_ pin becomes low. the ipbusy_/opact_ pin becomes high, when the sequence ends. when both the ip sequence and the op sequence are running, both the opbusy_/ipact and the ipbusy_/ opact_ pins become low. however, both pins are high in the initial state after a device reset operation, because nei- ther sequence is being executed. thus, the attributes and indications of the opbusy_/ipact and the ipbusy_/ opact_ pins change depending on the arbitration method. therefore, use careful with regard to the differences shown in table 4.3.1 and table 4.4.1.
4-13 address processor ke5b256b1 table 4.4.1 ipbusy_/opact_, opbusy_/ipact_ in external arbitration * device reset rst_pulse or srst command ** sequence pointer reset sqrst_pulse or ssqrst command power on *sp/tp_ p ull u p device reset devid sub- mode waiting state for ip/op sequence (no cpu, ip, op, and iop modes) ip sequence op sequence rd_pulse wr pulse sequence pointer reset** end of op sequence normal o p eration state sequence pointer reset** end of ip sequence tc sub-mode str_devid command end_devid command str_tc command end_tc command fig. 4.4.1 state diagram in external arbitration ipbusy_/opact_ opbusy_/ipact_ both ip sequence and op sequence are not running (initial state after device reset) h h ip sequence running h l op sequence running l h both ip sequence and op sequence are running ll
5-1 address processor ke5b256b1 fig. 5.1.1 word structure of cam 5. cam table the ke5b256b1 has a 256-kbit cam and stores the data table the searched in the cam. this chapter discusses the data table (cam table) construction and relation between searches and the cam table. 5.1 entry and segment the cam table is made up logically of many entries. in searching, part or all data of the entries are compared si- multaneously with all entries in the cam. as a device feature, the width (data bit of the entry) and number of the entries can be set flexibly. the entry is made up of 32-bit segments. accessing the cam table and searching operation are executed by segment unit. physically, one segment corresponds to one cam_word. the device has 8k (8,192)-cam_words and can store 256k-bit (32 x 8k) of entry data. each cam word is as- signed an absolute address (cam address) of 0h~1fffh (0~8192), and not only has segment data space for storing the entry data, but also has circuit elements for realizing some functions. fig. 5.1-1 shows all the elements comprising a segment. a detailed discussion is presented below. segment data the segment data stores the entry data. the width of one segment datum is 32 bits. the segment data can be used for cam or ram. the segment data operates as cam in the search operation. in table read/write, table maintenance, and outputting of search results, the segment data operates as ram. a definition of the distinction of cam/ram is not required. the methods of addressing when reading/writing segment data are (1) used the cam address (absolute address indi- cation) and (2) indication of the address by the segment number in the entry, using the entry address shown in the hha or hea register (discussed below) as an index. boundary bit the boundary bit is used for segment numbers (discussed below) and table configuration, and can be read or written only in the tc sub-mode. segment number the 3-bit width segment number indicates the number of the segment in the entry. the segment data can be read or written only in the tc sub-mode. 32 bits boundary bit empty bit segment data 1 bit 1 bit segment number access bit hit flag 1 bit 1 bit 3 bits
5-2 address processor ke5b256b1 in the search operation, the position to be searched is se- lected by indicating the segment number. when user ac- cesses the segment data as ram, they should select one segment of the entry by indicating the segment number. the segment number is determined by the hha register or the hea register with an index which is a segment number of the entry. the entry width and entry number of the cam table are determined by setting the boundary bit and the segment number. see for a section 5.2, table configuration detailed discussion of the setting sequences. empty bit the empty bit is a flag that indicates whether valid data is written in the segment or not (empty). the flag logic is shown below. 0: valid (valid data is written.) 1: empty (segment is a space.) when the empty bit is "1," the segment is not a search target. the empty bits of all the cam words are set to "1" after a device reset operation. the bit is reset to "0" when the corresponding segment is written. the conditions under which an empty bit is set or reset are presented below. set conditions (empty) ? device reset ? table configuration ? purge command reset conditions (valid) ? writing segment data ? restore command ? stamp command ? append command the empty bit can be read into the memar_at, memhha_at, and the memhea_at register. hit flag the hit flag indicates whether applied search key data is identical with the segment data being searched. the flag logic is shown below. 0: mis-hit (not identical) 1: hit (identical) the hit flag is an internal data, and cannot be read or written directly by register access, etc. access bit the access bit is a flag that indicates whether there are any previous hits in the search operation. the flag logic is shown below. 0: no hits. (no hit history) 1: one or more previous hits. (no less than one hit) the initial state of the access bit is "0." users can specify whether the hit history is held in the access bit during the search operation. the access bit is set to "1" when there is one or more hits after a search which is set to hold the hit history. the access bit holds "1" until an access bit reset operation (purge command or reset, etc.) is executed. when a purge command is executed with the access bit, entries which have not had hits can be purged collectively. a detailed discussion of the purge command function ap- pears in section 8.7. the access bit is basically set after the search operation and reset by command. however, the same operation can be also executed by accessing the memar_at, memhha_at, and memhea_at register. the access bit can be read through these registers.
5-3 address processor ke5b256b1 5.2 table configuration table configuration and cam table the cam table construction of the device can be defined flexibility by table configuration. there are eight varia- tions of the cam table configuration, as shown below. ? 32 bits x 8,192 entries (1 segment construction) ? 64 bits x 4,096 entries (2 segment construction) ? 96 bits x 2,728 entries (3 segment construction) ? 128 bits x 2,048 entries (4 segment construction) ? 160 bits x 1,636 entries (5 segment construction) ? 192 bits x 1,364 entries (6 segment construction) ? 224 bits x 1,168 entries (7 segment construction) ? 256 bits x 1,024 entries (8 segment construction) the above constructions are defined by setting the bound- ary bit and the segment number (tc data). the 8,192- cam word (0h~1fffh) is actually divided into four banks. the same configuration is necessary for all banks. in the case of one entry n segment construction, define the segment number cyclically (e.g. 0, 1, 2,???, n-1, 0, 1, ??? ) from the head cam word of each bank, and set the bound- ary bit of the segment number 0 word to "1" and the other words to "0." this operation concatenates the continuous n segments (segment number 0 ~ segment number n) as one entry. the concept of an entry in table configuration is shown in fig. 5.2.1. each entry can contain contents ex- tending across multiple segments. in this case, the entry number m of one bank becomes the maximum integer which satisfies the following formula. n x m < 2,048 (1 < n < 8) the total entry number of the four banks is 4m. when one entry is constructed of 3, 5, 6 or 7 segments, there are remaining segments in every bank. the segment number of the remaining segments must be set to 7h ("111"), and the boundary bit must be set to "0." it is necessary that the number of the remaining segments is in no case identical with the quotient obtained by division of the word number (8,192) by n because every four bank has the remaining segments. the device does not operate as a cam table without the table configuration. therefore, after power on and the device reset operation, table configuration is necessary before using the device. table configuration procedure the table configuration procedure is described below. first, write "n-1" value at the ww<2:0> bits of the cntl register. the value "n-1" is important when using the auto- matic increment function of the memhha register and memhea register, which are explained in chapter 8. at this time, the other bits of the cntl register must also be set to appropriate values for every setting of the device. a bit map of the cntl register is shown in chapter 13. move the tc sub-mode to write the tc data with the str_tc command. write the cam address in the ar reg- ister and the tc data in the cam table in the memar register. the bit maps of these registers are shown in chap- ter 13. the tc data must be set at all words of the four banks. when an entry comprises 3, 5, 6 or 7-segments, the remaining segments in each bank must be set (segment number "111," boundary bit "0"). in the cascaded systems, the same configuration is neces- sary for all devices. in this case, the broadcast writing method, which can write all devices simultaneously, is use- ful. the written tc data can be confirmed by reading the memar register in the tc sub-mode. escape to the tc sub-mode using the end_tc command after setting the tc data at all 8,192 words. at the end of table configura- tion, a frame of the table is complete, and all entries become empty. the gen_fl command must be executed immedi- ately after table configuration so that the device will rec- ognize the empty condition of all the entries. see chapter 8 and chapter 12 for a detailed discussion of the gen_fl
5-4 address processor ke5b256b1 fig. 5.2.1 concept of table configuration segment number (1 n 8) segment remaining segment n-1 01 entry number 0 entry number i entry number m-1 boundary 01 2 3 content(i,0) content(i,1) segment 32 bits bank 1 bank 2 bank 3 entry number m entry number 2m-1 entry number 2m entry number 3m-1 entry number 3m entry number 4m-1 bank 0 segment segment remaining segment remaining segment remainin g se g ment ? ? ? ? ? ?
5-5 address processor ke5b256b1 command. the construction of the tc data and the table in the 3-seg- ment configuration is shown in fig. 5.2.2. the table con- figuration procedure is shown in fig. 5.2.3. start segment and entry address every entry in the cam table is constructed with a single or plural segments. the start segment which has segment number "0" represents the entry, and unlike the other seg- ments, has the following some important roles. (1) entry address the address of the start segment is called the entry address, and is used to indicate the location of the entry. the hha register stores the highest priority (cam address is small) hit address. the hea register stores the highest priority empty entry address. it is necessary that the interval of the entry address is not "n" in 3, 5, 6, or 7-segment construc- tion because all banks have remaining segments in the gap between the banks. (2) empty entry the empty bit of the start segment indicates whether all entries are empty. when the empty bit of the start segment is "1," the whole entry is treated as empty and is not the object of a search. when the bit is "0" , the whole entry is valid. the empty bit of the start segment is cleared by writing the start segment, but the bit is not changed by writ- ing the other segments. the prg_ar command and re- store command must also be executed to the start seg- ment. when the stamp command is executed to the start segment, the entry becomes valid. (3) entry hit the access bit and the hit flag of the start segment repre- sent all entry hit information. when the object for a search is not the start segment, the search result is also indicated at the hit flag and the access flag of the start segment. the hha register stores the entry address (cam address of the start segment). the user should access the start segment when reading/writing an access bit using the memar_at register. (4) index the index is the entry address which is stored in the hha register and hea register. the entry being accessed can be selected by the index and the segment number of the entry. modification, appending, and purge operations for the seg- ment data can then be performed with case. priority as mentioned above, the address of an empty or hit entry is shown in the hha register or the hea register in the order of entry priority. therefore, entry priority is important for the device. the degree of priority is determined by the relation be- tween the entry and the physical device location. in the same device, an entry with a small address has high priority. in the same device, an entry which has a "0" entry address has the highest priority. in a cascaded system, the higher level devices of the system have higher priority. all entries of the higher level devices have higher priority than any of the entries of the lower level devices. see also the detailed discussion in chapter 9. 5.3 read/write segment data reading and writing the entry data are executed as reading and writing of segment data. the method of reading and writing segment data method is discussed below.
5-6 address processor ke5b256b1 (a) tc data fig.5.2.2 example of table configuration for one entry with three segments cam address boundary bit segment number 0 1 2 3 4 5 6 ? ? 2,043 2,044 2,045 2,046 2,047 1 0 0 1 0 0 1 ? ? 1 0 0 0 0 000 001 010 000 001 010 000 ? ? 000 001 010 111 111 bank 0 remaining segment 2,048 2,049 2,050 2,051 ? ? 4,091 4,092 4,093 4,094 4,095 1 0 0 1 ? ? 1 0 0 0 0 000 001 010 000 ? ? 000 001 010 111 111 bank 1 remainin g se g ment 4,096 4,097 4,098 4,099 ? ? 6,139 6,140 6,141 6,142 6,143 1 0 0 1 ? ? 1 0 0 0 0 000 001 010 000 ? ? 000 001 010 111 111 bank 2 remaining segment 6,144 6,145 6,146 6,147 ? ? 8,187 8,188 8,189 8,190 8,191 1 0 0 1 ? ? 1 0 0 0 0 000 001 010 000 ? ? 000 001 010 111 111 bank 3 remaining segment
5-7 address processor ke5b256b1 (b) table status after configuration fig. 5.2.2 example table configuration - for one entry with 3 segments (cont'd) - 012 entry number ? ? ? ? ? remaining segment bank 0 boundary segment number entry number ? ? ? ? ? remaining segment bank 1 boundary entry number ? ? ? ? ? remaining segment bank 2 boundary entry number ? ? ? ? ? remaining segment bank 3 boundary 0 1 2 681 682 683 684 1363 1364 1365 1366 2045 2046 2047 2048 2727 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
5-8 address processor ke5b256b1 fig. 5.2.3 example of table configuration for one entry with 3 segments ce_ 0ah 0ch 02h 0ch 00h 0ah 0ah 00h 0ch 00h 1h 01h 08h 23h 0h 1fffh 68h 07h 24h add<7:0> dat<15:0> writing cntl register writing the com register writing ar register writing tc data writing ar register writing tc data writing ar register writing tc data writing com register writing com register cntl register com register ar register memar register ar register memar register ar register memar register com register com register maximum segment number of one entry str_tc command end_tc command gen_fl command tc sub-mode
5-9 address processor ke5b256b1 cam address indication a physical address (0h~1fffh) is assigned to every seg- ment (cam word) . there are 3 address indication meth- ods, as described below. (1) absolute addressing by the ar register the segment can be selected by designating the cam ad- dress (0h~1fffh) using the ar address. the selected seg- ment data is accessed through the memar register. after setting the ar register, the segment data to be read can be executed by reading the memar register, and the writing of segment data can be executed by writing the memar register. (2) indexed addressing by the hha register the index is the entry address which is stored in the hha register. the segment can be selected by the index and the segment number of the entry. the selected segment num- ber is indicated by the cpuhs register. the selected seg- ment data is accessed through the memhha register. af- ter setting the cpu register, the reading of segment data can be executed by reading the memhha register, and the writing of the segment data can be executed by writing the memhha register. as a function of this addressing method, the segment num- ber or the entry address is incremental. creating table data and table maintenance are easy using this function. (3) indexed addressing by hea register the index is the entry address which is stored in the hha register. the segment can be selected by the index and the segment number of the entry. the selected segment num- ber is indicated by the cpuhs register. the selected seg- ment data is accessed through the memhea register. af- ter setting the cpu register, the reading of segment data can be executed by reading the memhea register, and the writing of segment data can be executed by writing the memhea register. as a function of this addressing method, the segment num- ber or the entry address is incremental. creating table data and table maintenance are easy using this function. a detailed discussion of setting of the cpuhs register in the case of the above (2) and (3) is presented in section 8.6 and chapter 13. endian function the width of the segment data is 32 bits, but the width of the cpu port data bus is 16 bits. therefore, two accesses are necessary to read/write the segment data. the device has an endian function that changes the upper and lower 16 bits of the memar, memhha, and the memhea regis- ter automatically when accessing these registers. this func- tion is enabled in default. a 32-bit read/write operation is executed every 2 times these registers are accessed. the ea bit of the cntl register indicates which register is accessed first. accessing is controlled by the endian- toggle-pointer. this toggle operation is executed when the memar, memhha, and memhea registers are read or written. therefore, when the upper or lower 16-bit word is only read or written, care is necessary regarding whether the next access object is upper or lower. the nap bit (next access point flag) of the devstat register indicates whether the next access object is upper or lower. basically, it is necessary to read or write both the upper and lower 16 bit word. however, if user wishes to access either the upper or lower word according to the contents of the segment data, it is necessary to access one side. in this case, the endian function is disabled by setting the eaoff bit of the cntl register to "1." when the endian function is dis- abled, the h/l toggle operation is not executed and one side is always accessed. the ea bit of the cntl register determines whether the object being accessed is upper or lower. when user wishes to change the fixed side, it is nec-
5-10 address processor ke5b256b1 essary to set the eaoff bit of the cntl register to "0" (endian function is on) , to set the eaoff bit to "1" ( endian function is off), and to select the h/l side using the ea bit. access by the endian function is also shown in fig. 5.3.1. when the following operations are executed, the toggle pointer is initialized according to the ea flag of the cntl register. ? device reset ? writing the ar register ? writing the cpuhsl register ? search operation (through the input port or cpu port) ? gen_hit command ? gen_fl command ? renewal of the hha register ? renewal of the hea register at series registers the confirmation of an entry empty bit can be executed by reading the at series registers (memar_at, memhha_at, and memhea_at registers). reading the empty bit is a read-only function, and is not able to write. a specified segment can be modified with the prg_ar command or the restore command. designation of the address of the segment is the same as with the memar, memhha, and the memhea regis- ters. all segments can be accessed using the at series reg- isters. in the tc sub-mode, the empty bit with the tc data can be read with the memar register. when the empty bit or reading/writing the access bit, read the start segment (segment number 0). 5.4 search and cam table a search operation is executed by one segment of the cam table. in one search operation, a 32- bit comparison can be executed by indicating the segment number to be searched. all segments which have the indicated segment number in the effective entries become the objects for search and are compared with the key data. this search operation can be completed in 80ns. in searches for multiple segments, user can use an and search operation. in the and search, the result, which is the and operation between previous search results and specified step of the search results, appears as the search result. for example, when user specifies the and search operation in the second search step, the entry which is hit in both first and second step is dealt with as the hit entry, and the hit flag of that start segment is set to "1." a detailed discussion of the search operation is presented below. the reader should refer to fig.5.4.1 for easier un- derstanding. this example is of one-entry 3-segment construction. a to- tal of two search operations are executed. in the first search operation, segment number 0 is indicated, and in the second search operation, segment number 2 is indicated as the search object. the and search operation is defined in sec- ond search operation. the key data 1 (32 bits) is input into the device through the input port or cpu port, and is used for the search operation. the upper bits of the segment are masked so that only part of "a1" is used for the search operation, and the device is defined to execute the search opera- tion with segment no. 0. in the first search operation, the entries which have segment data "a1" at the segment number 0 segment (entry no. 1, 2, 3) are hit, and hit flags of the start segments of every entry are set to "1." the hha register holds the hit entry address of the
5-11 address processor ke5b256b1 fig. 5.3.1 endian function endian toggle pointer ea bit 1 0 eaoff bit = 0:(toggle on*1) access object h ? l ? h ? l *2 l ? h ? l ? h *1 the toggle operation is executed by reading or writing the memar, memhha,and memhea register. *2 the endian to gg le function is on in the initial state after device reset, the user accesses the device start from the h side. eaoff bit = 1:(toggle off) ea bit 1 0 access object h ? h ? l ? l ? h side l side toggle 31 ? ? ? ? ? ? ? ? ? 16 15 ? ? ? ? ? ? ? ? ? 0 segment data (32 bits)
5-12 address processor ke5b256b1 highest priority (highest hit address) after the search operation is executed. in this example, the hha register holds the entry address ("3") of entry no. 1. the priority becomes higher in the upper device in cascaded devices, and becomes higher as the absolute address in the device becomes smaller. in the second search operation, key data 2 (32 bits) is introduced into the device as the search key data. segment no. 2 is defined as the search object, and the and search is defined. therefore, the second search key is "b1," and some of the entries (entry no. 0, 2, 3) which have "b1" at segment number 2 are hit. in this example, entry no. 2 and entry no. 3 are hit entries. user can execute the search operation for the plural seg- ments with key data which has many bits. as shown in this example, when the length of the key data is not a multiple of 32 bits, the search operation can be executed with data of any length using the mask capability. as the segment number for search is defined for every search operation in- dependently, the segment used for the and search opera- tion need not be close. if an and search operation is not indicated, a search result which is independent of the previous search result appears. the entries (entry number 0, 2, 3) which have the segment data "b1" at the segment no. 2 are hit when the and search is not defined in the second search step. in the case of a search operation through the input port (ip search), the segment number for the search is set at the ig<2:0> bits of the cs register, and in the case of a search through the cpu port (cpu search), it is set at the cg<2:0> bits of the cpusrs register. in the ip search operation, 8 search steps can be executed in one search sequence. users can define the segment number in every search step indepen- dently. bit maps of all registers are presented in chapter 13. the hha register has the address which is the highest pri- ority address (highest hit address) of the hit entries. in fig. 5.4.1, the entry address "3h" is stored in the hha reg- ister of the entry no.1 as the first search result. after the second search operation, the entry address "6h" of entry no. 2 is stored in the hha register. after a search operation, user can learn the address of the hit entry by reading the hha register. the segment of the hit entry can be accessed with an index which is the hha register. a detail discussion is presented chapter 8. the hha register has an address which is the highest prior- ity address (highest empty address) of the empty entries. in fig. 5.4.1, as entry no. 679 is the highest priority empty entry, the entry address "7f5h" of entry no. 679 is stored in the hea register. cam table maintenance, for example appending an entry, can be executed with an index which is the hea register. see chapter 8 for a detail discussion. as mentioned above, the device supports a mask capability for the key data, designating the segment for search in ev- ery search operation, and an and search operation. there- fore, the device can handle various search operations flex- ibly. the example here is for a 3-segment construction, but other cases are the same.
5-13 address processor ke5b256b1 fig. 5.4.1 search and cam table segment number 012 lsb msb search key data 1 ? upper bits are masked ? segment no. 0 and search search key data 2 ? segment number and search hstat register hha register msb lsb empty area b1 entry number entry address a1 a1 a1 entry no.0 0h entry no.1 3h entry no. 2 6h entry no. 3 9h entry no. 4 ch entry no. 678 7f2h entry no. 679 7f5h entry no. 680 7f8h entry no. 681 7fbh a1 b1 c1 6h hit, multi-hit, etc. hea register 7f5h search result entry no. 682 entry no. 2727 remaining segment remaining segment 1ffbh 1800h input port cpu port output port cpu port b1 b1 c2 c1 memhha register
6-1 address processor ke5b256b1 6. input port the input port is used for inputting the key data. the search sequencer starts with writing data into the input port (wr pulse input), and the maximum 8-step search op- eration is executed synchronously with the wr pulse auto- matically. this search sequence (ip sequence) can be pro- grammable for the key data formatting, the start search tim- ing, and the segment location for search. it also indicates the mask independently with every step. when the and search described in chapter 5 is defined, the search opera- tion for data over 32 bits can be executed. this ip sequence definition is called the ip sequence configuration. a detailed discussion of the ip sequence configuration and the ip sequence is presented in this chapter. 6.1 input port configuration the port width is 32 bits, but it can be configured to 16 or 8 bits. when 16 or 8 bits are configured, 16 or 8 bits on the lsb side of id<31:0> are used. in the case of 16 bits, id<15:0> is effective. in the case of 8 bits, id<7:0> is effective. a polarity of the wr pulse is pro- grammable. when the polarity is positive, the data on the id<31:0> is acquired to the internal buffer with the positive edge of the wr pulse. on the other hand, in the case of negative polarity, the data is acquired with a negative edge, and the search operation starts synchronously with the wr pulse. the width of the input port is defined by the iw<1:0> bits in the cntl register. the polarity of the wr pulse is defined by the wp bit in the cntl register. 6.2 ip sequence configuration two-channel structure the search sequencer of the input port is a 2-channel struc- ture which has an a channel (ach) and a b channel (bch), and two independent ip channels can be defined. these 2 channels can be used with changing channels. furthermore, when the multi-channel configuration which can define a maximum of 16 independent sequences is used, various search sequences can be executed, as shown below. since user can define plural sequences beforehand, there is no overhead operation which renews the configuration in changing configurations. the following registers define the ip sequence. these reg- isters are prepared for 2 channels. a maximum of 8 steps can be defined on every channel independently. ? cut register (cut0l/cut0h, cut1l/cut1h) ? ss register (ss0l/ssoh, ss1l/ss1h) ? cs register (cs0~cs7) ? mask register (mask0l/mask0h ~ mask7l/mask7h) for the above registers, both the ach register and the bch register are mapped at the same address. user can access the channel (inactive channel), which is not selected as the ip sequencer, by reading/writing these pointed registers. that is to say, when the ach is being used, the register of the bch can be accessed, and when the bch is being used, the register of the ach can be accessed. therefore, while one side of the channel is used, the other side of the channel can be defined. see section 6.3 for a detailed discussion.
6-2 address processor ke5b256b1 content of the configuration a detailed discussion of the ip configuration is presented in this section. ? cut through the data on the id bus is acquired into the device synchro- nously with the wr pulse according to the definition. the data which is acquired with one wr pulse, and whose width is defined as the input port width, is called one data block. the device has a function which acquires necessary data blocks as the ip sequence key data in a maximum of 64 data blocks. this function is called the cut through func- tion. user can define it in the 64-bit cut register (divided by the cut0l, cut0h, cut1l, and cut1h registers every 16 bits) according to which data block is acquired. there is an explanation of the cut through function in fig. 6.2.1 (a). this example shows that the input port width is 8 bits. the 8-bit data block, which is input with the first wr clock after the sequence reset operation, is treated as block 0 and the ct<0> bit of the cut register determines whether the data is acquired. similarly, every bit of the cut register corresponds to every data block. only the data blocks which correspond to the bit "1" are acquired. in this example, blocks 0, 2, 3, and 5 are acquired. fig. 6.2.2 shows the 16-bit width of the input port case and fig. 6.2.3 shows the 32-bit width case. they are the same as fig. 6.2.1 (a) except that the acquired data is 16 bits or 32 bits. ? data accumulation the data blocks acquired by the cut through function are stored into the 32-bit accumulation buffer in sequential or- der from the least significant bit. when the wr pulse is applied after the 32-bit accumulation buffer has no space in which new data blocks can be stored (buffer full), the content of the accumulation buffer moves into the sub- accumulation buffer and the newly acquired data block is stored on the lsb side. next, when the accumulation buffer is full, the acquired data block is stored in the higher side of the previous ac- quired data block. however, if the buffer is full, the data is stored on the lsb side of the accumulation buffer after the content of the accumulation buffer moves into the sub-accumulation buffer. after this, the operation is re- peated for every data block inputting. when the content of the accumulation buffer moves into the sub-accumulation buffer, the previous acquired data block is purged. the general process is called data accumulation, and is ex- ecuted in the device automatically with the data acquisition by the cut through function. fig. 6.2.1 (a) shows that the first acquired 4 data blocks (block 0, 2, 3, 5) are input into the accumulation buffer by 8-bit unit. when the 5th (block 7) data block is acquired, the content of the accumulation buffer moves into the sub-accumulation buffer, because the accumulation buffer has no space. data blocks after this block are ac- quired into the accumulation buffer in the same manner as the first four blocks. therefore, when the 6th block (block 9) is acquired, the status of the buffers becomes that as shown in fig. 6.2.1 (c). in the case of 16 bit data blocks (fig.6.2.2), and 32 bit data blocks (fig.6.2.3), the move into the sub-accumulation buffer occurs after every second data block acquisition (16 bit), and after each data block acquisition (32 bit). the accumulation buffer and sub-accumulation buffer have the newest 64-bit data. user makes the key data for the search operation with 32-bit selected data in the 64-bit data.
6-3 address processor ke5b256b1 (c) key data in second search operation (b) key data in first search operation (a) concept of the data formatting fig. 6.2.1 input data formatting example (input port width = 8bits) search key data (32 bits) 0-byte shift 1-byte shift 2-byte shift 3-byte shift search window msb lsb 0-byte shift 1-byte shift 2-byte shift 3-byte shift search window msb lsb search key data (32 bits) (8x64) bits input data stream : cut register 63 0 1 2 3 5 : ss register 1 1 1 1 1 1 62 1 data block (=8 bits) 1 1 search key data 32 bits = 1 segment 0-byte shift 1-byte shift 2-byte shift 3-byte shift search window msb lsb 6 7 8 9 8bits sub-accumulation buffer accumulation buffer 8bits 8bits 8bits 8bits 8bits 8bits 8bits 8bits sub-accumulation buffer accumulation buffer 8bits 8bits 8bits 8bits 8bits 2 0 8bits 8bits 2 0 8bits buffer accumulation buffer 8bits 7 9 3 5 0 2 7 9 3 5 sub-accumulation 4 1
6-4 address processor ke5b256b1 fig. 6.2.3 input data formatting example (input port width = 32bits) fig. 6.2.2 input data formatting example (input port width = 16bits) note: 64-bit data are stored in data blocks 2 and 3. however, definition of the search operation with the ss register occurs only one time. in this figure, the search key data stand on 2 data blocks. it is necessary to define the search window appropriately. (16x64) bits input data stream : cut register search key data 32 bits = 1 segment 0-byte shift 1-byte shift 2-byte shift 3-byte shift 63 0 1 2 3 4 5 : ss register 1 1 1 1 1 1 11 62 search window msb lsb 1 data block (= 16 bits) 1 1 (32x64) bits input data stream 8bits : cut register search key data = 1 segment 0-byte shift 1-byte shift 2-byte shift 3-byte shift 63 0 1 2 3 4 : ss register 62 search window msb lsb data block (= 32 bits) sub-accumulation buffer 1 11 1111 accumulation buffer 5 11 1111 8bits 8bits 8bits 8bits 8bits 8bits 8bits 8bits 8bits 8bits 8bits 8bits 8bits 8bits 8bits accumulation buffer sub-accumulation buffer 9 8 7 6 9 8 7 6
6-5 address processor ke5b256b1 ? search start the ss register points the timing the start search operation (search start). the ss register like the cut register, is a 64-bit width register (divided to the ss0l, ss0h, ss1l, and ss1h registers every 16 bits). the search operation starts when the data blocks which correspond to the bit lo- cation (defined as "1") of the ss register are input. in fig. 6.2.1 (a) bit 2 and bit 9 are set to "1." when either block 2 or block 9 is input, the search operation starts. as mentioned above, it is possible to execute up to the maximum 8-step search operation per one ip sequence. therefore, the number of bits which can be defined as "1" in the ss register can go as high as 8. as the ss register is a 64-bit register, user can define up to 8 as the search start timing in the 64 data blocks input timing. when the search operation starts according to the defini- tion of the ss register, the search operation is executed ac- cording to the definition of the following cs register and mask register. there is explanation about cut through, data accumula- tion, and search start again with referring to fig. 6.2.1 below. at first the block 0 is acquired with the first wr pulse. however, as the ss<0> bit of the ss register is not set to "1", the search operation is not executed in this time. when the block 2 is acquired with the 3rd wr pulse, and the ss<2> bit is set to "1," the first search operation is ex- ecuted. (see fig. 6.2.1 (b)) when blocks 3 and 5 are acquired with the 4th and 6th wr pulses, the accumulation buffer has no space. and when block 7 is acquired with the 8th wr pulse, the content of the accumulation buffer moves into the sub-accumulation buffer. block 7 is stored in the accumulation buffer at the same time. however, since as the bits of the ss register which correspond to these data blocks are not set to "1," the search operation is not executed. when block 9 is acquired with the 10th wr pulse, and the ss<9> bit of the ss register is set to "1," the second search operation is executed. (see fig. 6.2.1 (c)) see fig. 6.2.2 and fig. 6.2.3 in the case of the 16-bit width input port and 32-bit definition. as mentioned above, when the search operation starts ac- cording to the definition of the ss register, the search op- eration is executed according to the definition of the fol- lowing cs and mask registers. there are eight cs regis- ters (cs0 ~ cs7) and eight mask registers (mask0 ~ mask7). every register corresponds to sequences num- bered 0 ~ 7. the ip sequence pointer determines which search operation of the sequence number is executed. the pointer is increased with every search operation according to the bit of the ss register which is set to "1." the structures of the cs and mask registers in can be seen fig. 6.2.4. a detailed discussion of these functions with reference to fig. 6.2.4 is presented below. ? search window set the search window set is the function in which the 32-bit data for search is taken out from 64-bit data stored in the accumulation and sub-accumulation buffers. a 32-bit window is set to 64-bit data, and continuous 32- bit data is taken out as the key data. the location of the window can be define four kinds by byte unit. a detailed discussion of the search window set with refer- ence to fig. 6.2.1 (a) is presented. in the case of a 0-byte shift, 4-byte data is used as the search key data. in the case of a 1-byte shift, the lower 3-byte of the accumulation buffer and the upper 1-byte of the sub-accumulation buffer are selected. similarly, in the case of a 2-byte shift, the lower 2-bytes of the accumulation buffer and the upper 2-bytes of the sub-accumulation buffer are selected. and
6-6 address processor ke5b256b1 fig. 6.2.4 cs register and mask register in the case of a 3-byte shift, the lower 1-byte of the accu- mulation buffer and the upper 3-byte of the sub-accumula- tion buffer are selected. this function is useful to take out the data by adjusting a data gap, when the search key data stands among the input data blocks. the search window set is executed by setting the byte shifting byte number at the sw<1:0> bits of the cs register which corresponds to every search step. in fig.6.2.1 (b) and (c)), the sw<1:0> bits are set to "00" in order that the first search is set to the 0-byte shift mode. the sw<1:0> is set to "10" in order that the second search is set to the 2-byte shift mode. the making the key data, which is constructed with the cut through, data accumulation, search start, and search window set, is called data formatting. as the data made by the data formatting is stored in the cmp register of that data's sequence number, user can confirm the key data of every sequence by reading the cmp register. there are 8 cmp registers (cmp0 ~ cmp7) which correspond to the sequence numbers of every search operation. ? definition of the search segment the segment number of the search object can be defined with every search step in the ip sequence freely. any num- bers of the segment can be searched in any order by this function. the segment data of the defined segment number and the key data are compared among all effective entries in sequence pointer mask data search window set data search se g ment number end of sequence flag 1bit 3bits 2bits 16bits 32bits cs register maskh register maskl register (sequence number) (0) 16bits (1) (2) (3) (4) (5) (6) (7) 1bit 1bit access bit set fla g search head fla g mask register
6-7 address processor ke5b256b1 the data table by the definition of the search segment. the segment number can be defined from "0" to "number of segment per entry - 1." the definition of the search segment is executed by setting the segment number into the ig<2:0> bits of the cs regis- ter, which corresponds to every sequence number. ? mask data the mask operation is executed to the 32-bit search data, which is made by the data formatting, each bit according to the content of mask data definition. the bits whose corre- sponding mask data is "1" are not compared. the mask data is defined to the mk<31:0> bits of the mask register, which correspond to every sequence num- ber. in fig. 6.2.1, as the upper 16-bit of the accumulation buffer does not have the input data in the first search opera- tion of (b), the upper 16-bit location is necessary to be masked to protect the wrong search operation by unsettled data. in this case, the upper 16-bit of the mask data is all "1" and the lower is all "0." in second operation of (c), all the mask data is defined to "0" and the all 32-bit data is the object for comparison. ? search head and and search when the search key data is over 32 bits and the search object stand among plural segments, user executes the and search operation. in the and search operation a hit flag is set, if all result of search operations are hit. the and search operation in the ip sequence is defined with the head flag (ish bit) of the cs register. the search step whose search head flag is defined as "1" is executed independently with the previous search result. on the other hand, in the search step whose search head flag is defined as "0," the and search operation with the previous search result is executed. the hit result of the step in which the and search is defined is the and search result with the previous search results. user must set the search head flag to "1" in the first search step. the and search operation is defined as the series of search operations from the sequence number of the step whose search head flag is defined to "1," until the se- quence before the next "1" appears. some search head flags can be defined in the ip sequence. on the other hand, as the previous search result is purged by the search opera- tion whose search head flag is "1," in the case of confirm- ing the search result, user needs to take out the result be- fore the next search operation. ? access bit set the access bit means the past career of the hit results as described in chapter 5. the access bit set determines whether the search result reflects the access bits of every entry. when the access bit set flag (iac bit), which corresponds to the sequence number, is set to "1," each hit entry's ac- cess bits are set to "1." on the other hand, when the iac bit is set to "0," the access bit holds the previous state. the access bit which is set once is not cleared until the purge or rst_ac command is executed. using the career stored in the access bit, user can simulta- neously erase entries which have (or do not have ) careers of hit with a command for table maintenance (prg_nac or prg_ac). furthermore, when the and search is indicated, user needs to be careful about indicating the access bit. for example, if user indicates the and search to execute a 64-bit com- parison with 2 search operation and indicate the access bit set (iac = "1"), all access bits of entry which are hit en- tries at first search operation are set to "1." therefore, if the remaining 32 bits are not hit, the access bit holds the previ- ous status ("1"). as the result of this and search operation
6-8 address processor ke5b256b1 outputs after the 2 search operation, the user must set the access bit set (iac = "1") at only the second step. as mentioned above, when the and search operation is defined by indicating the access bit, user needs to set the access bit set (iac = "1") at the last step. ? end-of-sequence end of sequence is indicated with the end-of-sequence flag (eos bit) of the cs register. when the search step whose eos bit is set to "1" completes, the ip sequence completes. the wr pulses after the ip sequence are ig- nored. when the sequence pointer cannot detect the end- of-sequence (eos = "1"), the ip sequence cannot complete and there is the possibility of mis-operation. therefore, user must set the eos bit of the cs register to "1" corre- sponding to the fitted step. as mentioned above, after setting the cut through to the cut register, setting executing timing (the search start) to the ss register, and setting the content of every step to the cs, and mask registers, the ip configuration is com- pleted. multi-channel function as previously stated, as the cut, ss, cs, and mask reg- isters are prepared for both ach and bch, user can define 2 kinds of the ip sequence. the cs and mask registers have 16-step register in total (because of 8 steps x 2 channels). user can increase independent sequences up to 16 steps (fully independent in every step) maximum to use the de- vice effectively by dividing the sequence in the channels. this function is called a multi-channel function. the multi-channel function is realized by setting the se- quence number freely. the search step which is indicated by the sequence pointer is executed when the data block whose search start is indicated at the ss register is ac- quired. an initial value of the sequence pointer is called a sequence start number. the sequence start number is indicated by pins or a setting value of the register at the timing of the sequence pointer reset. the search operation is executed in order from the indicated step at every search start timing. and the se- quence pointer stops at the step at which the end-of-se- quence is indicated. the ip sequence is then complete. the configuration shown in fig. 6.2.5 is necessary to real- ize the multi-channel function. the end-of-sequence (eos= "1") is indicated at plural steps, and sequences are divided into independent sequences every end-of-sequence. for example, in this example if user selects sequence no. 2 of ach as the sequence number, 3-step of the sequence number of ach (no.2 ~ no.4) are executed as one search operation. if user selects sequence no. 5 of bch as the sequence number, sequence no.5 of bch is executed as one search operation. user can define the independent se- quences up to the number of the eos (max. 16) and uses them with changing. however, as the definition of the cut through and search start is common at every channel, the data block is ac- quired and the search operation is executed according to the definition of the ach cut and ss registers though any step of the ach can be selected as the sequence number. the bch is the same. for example, in the case of the example shown in fig.6.2.5, the sequence of ach is divided into three sequence blocks. if the two search starts are defined in the first sequence block which has two sequences, the device cannot execute the 3rd step (the sequence no.4) of the 2nd sequence block. as the device cannot recognize the eos of se- quence no.4 forever, the ip sequence cannot be completed. in the case of multi-channel configuration as shown in fig. 6.2.5, user needs to define "1" at the ss register which cor-
6-9 address processor ke5b256b1 fig. 6.2.5 ip multi-channel configuration responds to the maximum number of sequence step (ach => 3, bch => 4 in fig. 6.2.5). furthermore, a detailed description of the selection method of the channel and the start sequence number is presented in section 6.3. notice of the configuration be careful the following item in the configuration: ? the registers for the configuration which is not selected for sequence (active channel) cannot be accessed. but the opposite side can be accessed through the cpu port. user needs to be careful which channel is executing the configu- ration. ? the bits of the cut register must be set to "1" when the corresponding bits of the ss register is "1." (do not ex- ecute the search operation without the data block acquisi- tion.) ? set the maximum number of steps, which is defined at the same channel of the cs register, at the ss register. ? in the case of the and search operation, be careful where the access bit is. ? set the segment number for the search operation to the value which is indicated by the table configuration. if user uses the value which is different from the value as tc data, the operation is not guaranteed. in the case of 3, 5, 6, 7 segment structure, segment no.7 ("111") of the remaining segment cannot be used for the segment for the search op- eration. cs register mask register sequence no.0 sequence no.2 sequence no.3 sequence no.4 sequence no.5 sequence no.6 sequence no.7 0 0 0 0 1 1 1 1 cs register mask register sequence no.2 sequence no.3 sequence no.4 sequence no.5 sequence no.6 sequence no.7 1 1 1 0 0 0 0 0 eos eos a channel se q uence b channel se q uence channel select start se q uence no.select sequence no.1 sequence no.1 sequence no.0
6-10 address processor ke5b256b1 ? define the end-of-sequence with the appropriate step. ? as the channel and start sequence number can be defined freely if user indicates error channel/start sequence, it is possible to operate unexpectedly. as the registers for the ip sequence configuration have fixed initial values, we recom- mend user to configure unused registers strongly. 6.3 selection of channel and start sequence number channel selection there are two methods to select the active channel of the input port: ? hardware channel selection by the ipch pin ? software channel selection by the cntl register when user indicates the hardware channel selection, the active channel is selected by the ipch pin. the status of the ipch pin is latched into the device at the timing of the sequence pointer reset operation (low pulse for the sqrst_ pin or the falling edge of low pulse for the ce_ pin at the ssqrst command). when the latched signal is low level, a channel is selected. on the other hand, when the latched signal is high level, b channel is selected. if the signal on the ipch pin changes after the sequence pointer reset operation, but the channel changing does not occur. when user indicates the software channel selection, the ac- tive channel is selected by the definition of the ia<2:0> bits of the cntl register. the sequence pointer reset opera- tion after the register definition completes the channel se- lection. the sequence pointer reset operation is necessary after the register definition. the ias bit determines which above two methods is used. when this bit is "0," the software selection is selected. when this bit is "1," the hardware selection is selected. furthermore, the software selection is selected and the ac- tive channel is ach in its initial state after the device reset operation. in both cases the current selected channel can be confirmed by reading the ia<2:0> bits of the cntl, hstat, estat register. furthermore, the channel which is not se- lected can be accessed through the cpu port. the defini- tion of these registers can also be executed but not in the cpu mode. selection of start sequence number there are also two methods to select the ip start sequence number: ? hardware selection by the isnm<2:0> ? software selection by the cntl register when user selects the hardware selection, the start se- quence number is selected by the ipn<2:0> bits of the cntl register. this 3-bit defined sequence number is rec- ognized in the sequence pointer reset operation as the se- quence number. in both cases the current selected sequence number can be confirmed by reading the ipn<2:0> bits of the cntl regis- ter. when user changes the method of changing the channel and the start sequence number by writing the cntl register, the channel and the start sequence number must be recog- nized to the device by the sequence pointer reset operation and the new selection method.
6-11 address processor ke5b256b1 6.4 ip sequence operation sequence operation in the ip sequence the search step of every sequence num- ber is executed according to the ip sequence configuration described in section 6.2. the internal ip sequence pointer controls which search step of the sequence number is ex- ecuted. the ip sequence pointer is constructed with an increment counter. this counter is initialized to the above-mentioned start sequence number by the sequence pointer reset opera- tion (low pulse for the sqrst_ pin or issuing the ssqrst command) , and increases after one step of the search op- eration. the cut through and search start are also initialized by the sequence pointer reset operation. a right of control returns to the lsb bit of the cut register (ct<0>) and ss register (ss<0>) (the right of control returns to the ct<0> and ss<0> bit not according to the start sequence number.) the ip sequence starts with the first wr pulse after the sequence pointer reset operation. the data block is ac- quired according to the definition of the cut register, and the search step is executed one by one according to the definition of the ss register. one search step is executed at the timing of the wr pulse which corresponds to the defined "1" bit in the ss register. the search step, which has an identical sequence number with the sequence pointer, is executed according to the definition of the cs register and mask register. the value of the sequence pointer is increased by completion of the search step. therefore, the sequence number which is ex- ecuted next is one step forward of the previous step. the search step is executed in order by repeat repeating the same process. after completion of the search operation which is defined in the cs register, the pointer stops and the ip sequence is complete. user can confirm which sequence number is complete by the is<2:0> bits of the devstat register. the wr pulses after the ip sequence completion are ignored until the se- quence pointer reset operation is executed again. search results the search results are reflected in the four pins (ho_, po_, sh0_, sh1_) and five registers (cmp, hstat, hha, memhha, sh). a description of the search results which is indicated by the pins or the registers is presented below. output pins ? ho_ pin after the search operation, if a hit occurs, this pin outputs low level, and if no hit occurs, this pin outputs high level. furthermore, this pin is not initialized by the sequence pointer reset operation and holds the previous status by the next search operation. ? po_ pin after the search operation, if there is a multi-hit entry, this pin outputs low level, and if there is no multi-hit entry, this pin outputs high level. furthermore, this pin outputs the devid priority signal in the devid sub-mode. this pin is not initialized by the sequence pointer reset operation and holds the previous status by the next search operation. ? sh1_, sh0_ pins these pins output the results of the specified sequence number. the shasgen register determines the sequence number in which the search results are output. user can define the independent sequence number in the sh0_ or sh1_ register. each pin outputs low level if the result of
6-12 address processor ke5b256b1 the defined sequence number is hit, and becomes high im- pedance if no hit occurs (open drain output). in the case of the and search, each pin outputs the and search results to the defined sequence number. furthermore, the sh0_ and sh0_ pins are initialized to a high impedance state by the sequence pointer reset opera- tion. fig. 6.4.1 shows an example of an ip sequence process and a change of the above flag's outputs. in this example, the input port is 16-bit width, the wr pulse polarity is nega- tive, and the cut and ss registers are defined to acquire data blocks 1, 2, 4, 5, 6, 7 and to execute the search opera- tion at the timing of data blocks 2, 5, 7. sequence no.2 is indicated as the start sequence number, and sequence no.4 is indicated as the end-of-sequence number. furthermore, the sh0_ is defined to output the search result of sequence no.2 and the sh1_ is defined to output the search results of the sequence no.4 in the shasgen register. the ip sequence is occurred by the first wr pulse after the sequence pointer reset operation. the opbusy_/ipact_ pin changes to low level. this means that the ip sequence has started. (when the sp/tp_ pin is low, this means that the mode is the ip mode.) the sequence is executed syn- chronously with the wr pulse and every search operation is executed with the 3rd, 6th, and 8th wr pulses. the ho_ and po_ pins change according to this operation. on the other hand, the sh0_ and sh1_ pins change only in the indicated sequence number. the sh0_ pin is initialized to a high impedance state with the sequence pointer reset operation. it outputs the search results after the sequence no.2 search step is executed with the 3rd wr pulse, and holds the results. when the sequence no.4 step is executed with the 8th wr pulse and holds the result after this, the sh_1 pin changes in the same manner as the above sh0_ pin. the ho_ pin changes when the next search operation is executed. however, the sh0_ and sh_1 changes, when the specified sequence number is ex- ecuted, hold the results. therefore, these pins are useful for monitoring the middle results. the ip sequence operation completion is indicated when the sequence operation is complete with the 8th wr pulse and the opbusy_/ipact_ pin becomes high level. (in case sp/tp_ = "0," the device returns to the iop mode.) ac specification of every flag is presented in chap- ter 14. a description of opbusy_/ipact_ changing timing is presented here. in the start of the ip sequence, the opbusy_/ipact_ changes with the first edge of the wr pulse. (wr pulse polarity = negative: negative edge; wr pulse polarity = positive: positive edge) on the other hand, two methods for changing the opbusy_/ipact_ pin in the end of the ip sequence are defined below: (1) with the first edge of the wr pulse (2) with the second edge of the wr pulse the second edge of the wr pulse is the positive edge when the wr polarity is negative, and is the negative edge when the wr polarity is positive. in the case of (1) above, user can always monitor the opbusy_/ipact_ signal with the first edge of the wr pulse. however, when the opbusy_/ipact_ becomes high level, the ip sequence is not fully complete. it shows that the ip sequence will be complete with this cycle. in the case of (2), the opbusy_/ipact_ pin becomes high level, and the sequence is fully complete. select this method if user wishes to control the rd_ signal with the opbusy_/ipact_ pin. the busy bit of the cntl register determines which method user selects. when this bit is "1," method (1) is selected, and when this bit is "0," method (2) is selected.
6-13 address processor ke5b256b1 *1 ssqrst command can be also executed. *2 in case of designating start sequence no.2(a-ch) by hardware selection. *3 wr polarity is negative. *4 input port width is 16 bits. (id<31:16> is don't care) *5 the results are output every search operation.(ac characteristic of ho_pin is different from po_'s. see chapter 14for deta ils.) *6 sh0_pin is defined as hit/miss hit of sequence no.2. sh1_pin is defined as hit/miss hit of sequence no.4 *7 busy bit of the cntlh register is "1." *8 busy bit of the cntlh register is "0." fig.6.4.1 ip sequence operation timing example *1 *2 sequence no.2(a-ch) ct<0>=0 ss<0>=0 ct<1>=1 ss<1>=0 ct<2>=1 ss<2>=1 ct<3>=0 ss<3>=0 ct<4>=1 ss<4>=0 ct<5>=1 ss<5>=1 ct<6>=1 ss<6>=0 ct<7>=1 ss<7>=1 a b cd e f ba dc fe first search sequence no.2 second search sequence no.3 third search sequence no.4 valid valid valid valid valid valid valid valid *7 *8 cut,ss register setting sqrst_ ipch,isnm<2:0> wr *3 id<15:0> *4 internal key data ho_ *5 po_ *5 sh0_ *6 sh1_ *6 opbusy_/ipact_
6-14 address processor ke5b256b1 register outputs ? cmp register the 32-bit key data, which was used in every search step after the formatting operations, is stored in cmp0 - cmp7, depending on the ip sequence number. ? hstat register after the search operation it stores hit in the device, multi- hit in the device, hit in the cascaded system, and multi- hit in the cascaded system, etc. ? hha register after the search operation it stores the hit entry address with the highest priority. ? memhha register user can read the segment data, which is stored in the entry address indicated by the hha register, by outputting the memhha register. ? sh register the device-search results of each step in the ip se- quence are stored. if the defined sequence number ex- ecutes the and search operation, the sh register stores the results of the and search by each sequence number. a detailed bit map of the above mentioned register is pre- sented in chapter 13. the content of the hstat and hha register are rewritten in each search operation, and the con- tent of the sh register changes by one bit according to the sequence number. in this example, after the search step se- quence no.2 is executed, the cmp2 stores the formatted key data. after the search step sequence no.3 is executed, the cmp3 stores the formatted key data. after the search step sequence no.4 is executed, the cmp4 stores the for- matted key data. the above registers except the sh register can be output through the output port or the cpu port. user can get the information by the op sequence with the rd_ pulse or by reading registers with the ce_ pulse. the sh register can only be read by the device select operation through the cpu port. it is necessary to assert the rd_ pulse and ce_ pulse for outputting these registers with satisfied recovery time to the wr second edge (min. 20ns) after the input port cycle time (min. 80ns). if the rd_ or the ce_ pulse do not sat- isfy this condition, there is no effective result. ac specifica- tions about between the wr pulse and the rd_ pulse or the ce_ pulse are presented in section 14. the memhha register cannot be accessed through the cpu port without not moving to the cpu mode when the sp/tp_ pin is pulled down. when the sp/tp_ pin is pulled up, an external arbitration between the wr_ pulse and the ce_ pulse is necessary to protect the cam data destruction. restarting and suspending the ip sequence as mentioned above, when the ip sequence is complete, the ip sequence pointer stops and does not receive the wr pulse. if user wishes to start the ip sequence again, execute the sequence pointer reset operation. and if user wishes to suspend the ip sequence, execute the sequence pointer re- set operation. at this time, it is necessary to keep the re- covery time (min. 20ns) from overlapping the wr pulse on the sqrst_ pulse (or ce_ pulse of the ssqrst com- mand). in the case of internal arbitration with the sp/tp_ pulled down, there is a case in which the above timing cannot be kept because the wr signal does not synchronize with the ce_ signal in the external of the device. in this case, ex- ecute the cpu interrupt with the swcpup_im command.
6-15 address processor ke5b256b1 it suspends the ip sequence from the next wr pulse cycle. however, in this time, if there is no wr pulse, the device does not recognize and execute the cpu interrupt. there- fore, user needs to suspend the ip sequence with the se- quence pointer reset operation. 6.5 hha automatic output the device can output the content of the hha register on the od<31:0> bus automatically as an optional ip se- quence function in the ip sequence. it is called an hha automatic output function. this function is enabled by set- ting the hhasgn register. it enables user to get the hha output without applying the rd_ pulse to the output port in the ip search operation with the wr pulse. the content of the hhah (device id) is output on the od<31:16> and the content of the hhal (hha in the device) is output on the od<15:0>. a description of the bit map is presented in chapter 13. when the oe_ signal is high level, the od<31:0> bus be- comes high impedance not according to the hha auto- matic output mode. when the oe_ signal is low level and the hha automatic function is enabled and hit occurs, the hha is output. in the case of a cascaded system, the only device which has hit outputs the hha. however, when the oe_ signal is low level, every bit of the od<31:0> is not always driven to high or low level. when using this function, user has to use the device basi- cally in an application which has only a single hit, because when the multi-device has the hits, the output confliction on the od<31:0> bus occurs. and in the case of using the and search operation which searches for plural segments in the ip sequence, it is possible that a multi-hit will occur in the middle of the sequence. therefore, user has to define the hha automatic output sequence number. user defines the ipha<7:0>, ophb<7:0> bits of the hhasgn register corresponding to the ip sequence number of the hha au- tomatic output. for example, if the ipha<0> bit is set to "1," the hha automatic output is executed in the sequence no.7 of the a channel. see chapter 13 for a bit map of the hhasgn register. fig. 6.5.1 shows the timing of the hha automatic output. the hha automatic output function is defined in sequence no.7 and no.2, and every sequence has hits. as the hha automatic output function is not defined in sequence no.0, the output of the od<31:0> is high impedance, though the oe_ signal is low level. as the hha automatic output function is defined in sequence no.7 and no.2 and hits oc- cur, the hha is output on the od<31:0> bus. if there is no hit in this case, the output is high impedance. the hha output holds the current status until the next search opera- tion is executed or the op sequence is executed. the hha is output while oe_ is low level. basically, the hha automatic output function is defined only in the sequence number which is expected to have a single hit. however, user can control the oe_ pin exclu- sively by monitoring the ho_ pins output of every device, and the chance of a single chip multi-hit occurring is not a problem (the highest priority hit entry address of the de- vice is output.) in spite of the hha automatic outputting, control of the output port is changed in the device to output the defined op sequence data when the op sequence starts with the rd_ pulse. set all the ipha<7:0>, iphb<7:0> bits of the hhasgn register to "0" when not using the hha automatic output function. as the device reset operation initializes the hhasgn register to "0000h," this function is disabled in the initial status.
6-16 address processor ke5b256b1 fig. 6.5.1 hha automatic output sequence no.0 sequence no.1 valid valid valid valid valid wr id<31:0> oe_ od<31:0> *1 *1 hha automatic output in the sequence no.1 and no.2 sequence no.2
7-1 address processor ke5b256b1 7. output port the output port is the port for outputting search results. the output port has a sequencer, as does the input port. the op sequencer starts to output the search results to od<31:0> according to defined procedure, when the rd_ pulse is applied after an ip sequence or a search through the cpu port. the ap can output hit status, hit entry ad- dress, hit entry data, and search key data used in either the ip sequence or in the op sequence. the defining of the results which are output and the number of the results which are output is called the op sequence configuration. in this chapter, both the op sequence configuration and how the op sequencer works are explained. 7.1 op sequence configuration two-channel structure two independent, different op sequences can be defined, because the op sequencer also has a two-channel struc- ture (ach/bch) similar to the ip sequencer. these two op sequences can be selected at any time. more than three se- quences can be defined and executed using the multi-chan- nel configuration. the multi-channel configuration can be used with specifying the start sequence number like the ip sequence. plural sequences can be defined in advance, there is no overhead process like reconfiguration when the sequence is changed. the following two registers relate to the definition of the op sequence. these registers are prepared for two chan- nels, and eight step sequence in maximum can be defined independently for two channels. aoc register (aoc0 - aoc7) aosc register (aosc0 - aosc7) these two registers for ach and bch are mapped in the same address. when the registers of these address are read/ written, the registers of the unselected channel are read/ written. the op sequence of the unselected channel can be defined even while the op sequence of the selected chan- nel is executed. see section 7.2 about channel selection. configuration the assignment of the aoc and aosc registers for op sequence definition are shown in fig. 7.1.1 and fig. 7.1.2, and examples of the op sequence configuration are de- scribed below. selecting search results for output the search results can be output to od<31:0> as the data of five registers, the cmp register, hstat register , hha register, memhha register, hha & memhha register. the information about the register to be output is regis- tered to the aoc registers. there are eight aoc registers, aoc0 to aoc7, and each register corresponds to the op sequence numbers 0 to 7 respectively. the or<7:0> of each aoc register determines the ad- dress of the register to be output. (for example , 90h is set to output the hstat register.) according to these con- figurations, search results are output from the output port step by step. the sequence number to be executed is pointed by the op sequence pointer, and the op sequence pointer is incremented as each step of the op sequence is executed. the initial value of the op sequence pointer (the op start sequence number) can be selected from 0 to 7, and the explanation of this function is described later. the explanation of each register which stores search re- sults is described below: (1) cmp register (address: a0h, a2h, ... , aeh) the key data used in each step of the ip sequence is stored.
7-2 address processor ke5b256b1 register to be output cmp register hstat re g ister hha re g ister memhha re g ister hha & memhha re g ister one/all_fla g mixin g method(mx1,mx0) end of sequence fla g (eos) 8 bits 1 bit 2 bits 1 bit (sequence number) (0) (1) (2) (3) (4) (5) (6) (7) sequence pointer aoc register 1 bit 2 bits (0) (1) (2) (3) (4) (5) (6) (7) aosc re g ister 3bits (sub-sequence number) sub-sequence pointer segment number to be output mixing method (mxs1,mxs0) end of sub-sequence fla g (eoss) fig.7.1.1 aoc(automatic output control)register fig.7.1.2 aosc(automatic output sub-control)register
7-3 address processor ke5b256b1 (2) hstat register (address : 90h) four kinds of search result information are stored: hit in the device, multi-hit in the device, hit in the cascaded sys- tem, multi-hit in the cascaded system, and information on the active channel of the ip/op sequence. the hstat register can be mixed with the output data of other regis- ters (cmp, hha, memhha, hha&memhha regis- ters). (3) hha register (address: 94h) the hit entry address with the highest hit priority is stored. (4) memhha register (address : 0eh) the content of the hha entry is stored. the aosc regis- ter specifies the segment number in an entry to be output. the segment number specification is described in a later section. (5) hha&memhha register (address : b0h) the hha register and memhha register are output in turn if the address b0h of the hha&memhha register is set in the aoc register. the content of the hha register is output first and then that of the memhha register is output for each entry. the aosc register specifies the seg- ment number in an entry to be output. the hha&memhha register is provided for operation with automatic search result output through the output port. it cannot be accessed through the cpu port. in one series of the op sequence, only one of the three registers, the hha, memhha, and hha&memhha registers, can be defined in the aoc registers. in order to specify the registers, which have the individual address for each of the 16 bits of the lsb/msb side, the address on the lsb side (smaller address) must be speci- fied. the address of the hha&memhha register is b0h. one/all_ flag one search result is normally output for one read out cycle of one sequence number of the aoc register. when the memhha register, the hha register or the hha&memhha register is set in the aoc register, it is possible to select whether one or all of the hit entries should be read out. this is done by setting the one/all flag in the aoc register. if the one/all_ flag is set to "0," "all," all hit ad- dresses or all contents of the hit entries are output accord- ing to hit priority. the op sequence pointer is not incremented while there are any hit entries remaining in the cam table. after the output corresponding to a hit entry is completed, the data in the hha register is shifted to the next higher hit address, and accordingly, the data in the hstat register and the outputs of the ho_ and po_ pins are renewed. in the last output cycle, ho_ becomes high level, indicating an output of the all hit entries, and the op sequence pointer is incremented. if the one/all_ flag is set to "1," "one," the op se- quence pointer is incremented after one hit entry, which has the highest hit priority, is output. it should be noted that the data in the hha register is shifted, and the data in the hstat register, along with the outputs of the ho_ and po_ pins are also renewed in this case. in the case of a single hit, the behavior of the op sequencer is the same whether the one/all_ flag is "0" or "1." the one/all_ flag must be set to "1" for the hstat register and the cmp register output, because there is no "all output" for these registers.
7-4 address processor ke5b256b1 output segment number the aosc register specifies which segment in the hha should be read out if the memhha register or hha&memhha register is set in the aoc register. there are eight aosc registers, aosc0 to aosc7, and each register corresponds to the op sub-sequence number 0 to 7 respectively. eight segment numbers can be speci- fied at the most. the control of the op sequence moves to the sub-se- quence, which is defined by the aosc register, when the op sequence goes on to the step involving either the memhha register or the hha&memhha register. the op sequence number is not incremented until the sub-se- quence is completed. the sub-sequence number to be ex- ecuted is indicated by the op sub-sequence pointer, the op sub-sequence pointer is incremented as the rd_ pulse is given. the initial value of the op sub-sequence pointer can be selected from 0 to 7, the explanation of which is described later. the op sub-sequence pointer starts from the start sub-se- quence number and counts up to the sub-sequence number in which the sub-sequence end (described later) is set. if the one/all_ flag in the aoc register is set to "one," the op sub-sequence is completed and the incrementation of the op sub-sequence pointer is stopped at the sub-se- quence number in which the sub-sequence end is set. then, the control goes back to the op sequence defined by the aoc register and the op sequence number is incremented. if the one/all_ flag in the aoc register is set to "all," the op sub-sequence continues until the steps between the start sub-sequence number and the sub-sequence number in which the sub-sequence end is set are executed for all hit entries. the op sub-sequence pointer goes round between the start sub-sequence number and the sub-sequence num- ber in which the sub-sequence end is set. the op sub-se- quence is completed and the incrementation of the sub-se- quence pointer is stopped when the sub-sequence number in which the sub-sequence end of the last hit entry is ex- ecuted. then the control goes back to the op sequence de- fined by the aoc register, and the op sequence number is incremented. the content of the hha is output first and then that of memhha (segment data), which is specified by the aosc registers, are output for each entry, if the hha&memhha register is specified in the aoc regis- ter. mixed output of hstat register the hstat register can be mixed with the upper 10 bits of output data (od<31:28> and od<27:22>) when the register except the hstat register is output. table 7.1.1 shows how the hstat register is mixed by mx<1:0> of the aoc register or by mxs<1:0> of the aosc register. mxs<1:0> of the aosc register is given priority when the memhha register is set in the aoc register. mx<1:0> is used for hha output and mxs<1:0> is used for memhha output, when the hha&memhha register is set in the aoc register. end of op sequence the end of the op sequence is specified by the end-of- sequence flag (eos bit) in the aoc register. the end of the op sub-sequence is specified by the end-of-sub-se- quence flag (eoss bit) in the aosc register. if the eoss bit in the aosc register is set to "1," the step where the eoss bit is set to "1" is the end point of the sub- sequence, the sub-sequence end. when the step that the eos bit is set to "1" is completed, the op sequence is ended. if the output register of that step is memhha or hha&memhha, the op sequence is ended when the op sub-sequence is completed. if the one/all_ flag is set to "all" in that step, the op sequence is ended when the output for all hit entries is completed. after the op se- quence is ended, the rd_ pulse is ignored. the eos bit and the eoss bit must be set to "1" in a suit-
7-5 address processor ke5b256b1 *1 the data specified by the aoc register or the aosc register is output. table 7.1.1 mixed output specified by aoc register or aosc register able aoc register and a suitable aosc register. because the ap might not work correctly, the sequence end and the sub-sequence end cannot be detected. the eoss of the aosc register must be set to "1" for a start sub-sequence number if the memhha register and hha&memhha register are not set in the aoc registers. the op sub-se- quence pointer must be pointed to the op sub-sequence end if the op sub-sequence is not used , because the op sequence is ended when the op sequence end and the op sub-sequence end are detected. if the op sequence is not used, it is recommended to set the op sequence end and the op sub-sequence end to avoid the situation that the op sequence is started accidentally with the rd_ pulse given by mistake and not ended. multi-channel configuration the aoc register and the aosc register are prepared for ach/bch respectively as previously described, two op se- quences can be defined. there are 16 registers (8 steps x 2 channels) for the aoc register and the aosc register re- spectively, and multi-channel channel configuration can be set in the op sequence as the ip sequence multi-channel configuration. the op sequence multi-channel configuration is realized by setting the start sequence number and the start sub-se- quence number. once the step which is indicated by the sequence pointer (or the sub-sequence pointer) has been executed, the initial value of the sequence pointer is named the start sequence number, and the initial value of the sub- sequence pointer is named the start sub-sequence number. the start sequence number and the start sub-sequence number are set to the sequence pointer and the sub-se- quence pointer respectively at the sequence pointer reset. the step of the start sequence number is executed and the pointer is incremented when the first rd_ pulse is given. likewise when step which is indicated by the sequence pointer is executed and the pointer is incremented as the rd_ pulse is given. if the sequence pointer comes to the step to output the memhha register, the sequence pointer stays at that step and the sub-sequence is started from the initial pointer of the sub-sequence number. the segment data specified by the aosc register is then output bits of hstat register mixed to output port data mx1 (mxs1) mx0 (mxs0) od<31> od<30> od<29> od<28> od<27:25> od<24:22> 00 0 0 1 1 1 1 not mixed*1 not mixed*1 not mixed*1 op active channel ip active channel system hit system hit system multi-hit system multi-hit device hit device hit device multi-hit device multi-hit op active channel ip active channel
7-6 address processor ke5b256b1 fig. 7.1.3 op multi-channel configuration and the sub-sequence pointer is incremented as the rd_ pulse is given. when the sub-sequence pointer comes to the step in which the sub-sequence end is set, the sub-se- quence is completed and the sequence pointer is moved to the next step. when the sequence pointer arrives at the point where the sequence end is set, the sequence pointer is stopped and the op sequence is ended. the configuration shown in fig. 7.1.3. is needed to use the multi-channel configuration. the sequence end is set to more than one step, and the sequence is separated to plural independent sequences by the sequence end. the sub-se- quence is also separated by the sub-sequence end. various output can be achieved by the combination of the se- quences and the sub-sequences. if the sequence number 0 of the ach is selected as the start sequence number, as in the example of fig. 7.1.3, the two steps from the sequence number 0 to 1 are executed as one sequence. in this case, the sub-sequence is not used be- cause the step to output the memhha register or the hha&memhha register is not included in the sequence. if the sub-sequence is not used, the sub-sequence end must be set in the aosc register of the start sub-sequence num- ber to be detected at the start. in this example, the sub- sequence end must be set in the aosc0 register (or one of aosc2, aosc4, aosc7). the hstat register is output as defined in the aoc0 register when the first rd_ pulse is given, and the hit entry address of the highest priority is output as defined in the aoc1 register when the second rd_ pulse is given. the next priority hit entry address is output while hit entries exist with rd_ pulse, because the all_/one_ flag of the aoc1 register is set to "all." the op sequence is ended when the lowest priority hit en- try address is output. only one entry of memhha is output if the start se- quence number is set to 2 and the start sub-sequence num- ber is set to 1. because the aoc2 register specified to out- put memhha is set to "one," the segments specified by the aosc1 register and the aosc2 register are output. the segment number 0 is output with the first rd_ pulse and the segment number 1 with the second rd_ pulse. if another start sub-sequence number is selected for the same start sequence number , the segments in different order can be output. if the start sequence number is set to 3 and the start sub- eos output register 0 1 1 1 1 0 0 0 hstat(one) hha(all) memhha(one) hstat(one) hha&memhha(all) cmp2(one) op sequence number op sequence pointer a ch b ch aoc register 0 1 2 3 4 5 6 7 eoss output segment segment no. 0 1 segment no. 0 2 segment no. 0 1 2 1 1 1 1 0 0 0 0 0 1 2 3 4 5 6 7 op sub-sequence number op sub sequence pointer cmp0(one) a ch b ch aosc register cmp1(one) *1 *2 *3
7-7 address processor ke5b256b1 sequence number is set to 3, the hstat register is output at first, followed by the highest priority hit entry address, then the segment data of the entry is output in the order of segment 0, segment 2. the address and the segment data of hit entries are output repeatedly until the lowest priority hit entry is output because the aoc4 register specified to out- put the hha&memhha is set to "all." finally, the cmp2 register is output and the op sequence is ended. see the next section for the procedure to select the channel, the start sequence number, and the start sub-sequence number. remarks at configuration only the inactive channel registers of the configuration registers of the op sequence (aoc, aosc) can be ac- cessed from the cpu port. the sequence end and the sub-sequence end must be set at the appropriate step. if the op sub-sequence is not used (not output the memhha and hha&memhha), the start sub-se- quence number must be set to the sub-sequence number that the sub-sequence end is set. if the op sequence is not used, it is strongly recommended that the start sequence number be set to the step that the sequence end is set, and the start sub-sequence number is set to the step that the sub-sequence end is set. if the hstat register or the cmp register is specified to be output at a step in the op sequence, the one/all_ flag must be set to "one." only one of the hha registers, the memhha register, the hha&memhha register can be output in one op se- quence which is divided by the sequence end. unexpected action will occur if the wrong channel or the wrong start sequence number is selected. it is strongly recommended to set value to all the registers for the op sequence configuration if some of the registers are not used, because the registers for the op sequence configura- tion don't have the initial value. 7.2 selection of channel and start sequence number channel selection there are two methods of selecting the active channels (ach or bch) of the output port as follows: hardware channel selection by the opch pin software channel selection by the cntl register hardware channel selection is used to select the active channels by opch inputs. the states of opch is regis- tered at the sequence pointer reset (at the falling edge of sqrst_ or at the falling edge of ce_ when an ssqrst command is executed). if the registered signal is low then ach is selected, if the signal is high then bch is selected. the selected channels are not changed until the next se- quence pointer reset is executed by an sqrst_ low pulse or an ssqrst command. software channel selection is used to select the active channel by the oa<2:0> in the cntl register. software channel selection is completed when sequence pointer reset is done after the cntl register is set. sequence pointer reset must be done after the cntl register is set. whether hardware or software channel selection is used is determined by the oas in the cntl register. software channel selection is used when the oas bit is "0," hard- ware channel selection is used when the oas bit is "1." after device reset, software channel selection and ch-a are selected as the initial value.
7-8 address processor ke5b256b1 the currently selected (active) channel of the output port can be confirmed by reading the data of the oa<2:0> in the cntl, hstat or estat registers regardless of the method of selecting the active channel. the registers for the op sequence configuration of the inactive channel can be accessed through the cpu port in the cpu mode and another mode. start sequence number selection and start sub-se- quence number selection there are two methods to select the op start sequence number and the op start sub-sequence number. it should be known that these methods are different from the meth- ods to select the ip sequence number. ? start sequence number and start sub-sequence number are set to "0" ? numbers defined in the cntl register are used as the start sequence number and the start sub-sequence number the signal level of the opns pin selects which method is used. if the opns is low, the op sequence starts from se- quence number 0 and sub-sequence number 0. if the opns is high, the opn<2:0> of the cntlh register is used as the start sequence number and the opns<2:0> of the cntlh register is used as the start sub-sequence number at op sequence start. the opn<2:0> and opsn<2:0> bits of the cntlh regis- ter are "000" at the initial point after device reset. if these bits are not written after the device reset, the start sequence number and the start sub-sequence number are both 0 in spite of the signal level of the opns pin. the sequence pointer reset must be done after the channel selection method, or the selection method of the start se- quence number is changed by writing to the cntl regis- ter. the new selection method of the channel or the start sequence number is recognized at the sequence pointer re- set. 7.3 op sequence operation the op sequence pointer and the op sub-sequence pointer are reset by the sequence pointer reset (sqrst_ pulse or ssqrst command) in the op sequence in the same man- ner as in the ip sequence. the initial values of the op se- quence pointer and the op sub-sequence pointer are the start sequence number and the start sub-sequence number respectively. the first rd_ pulse after the sequence pointer reset starts the op sequence. the op sequence is executed in the order of the sequence number from the start sequence number and output data defined in the aoc register, to od<31:0>. the op sequence ends when the step for the sequence end, which is set in the aoc register, has been executed. the rd_ pulse is ignored after the end of the op sequence until the sequence pointer reset is executed. invalid data is output according to the op sequence defini- tion when the search result is mishit. once the op se- quence starts, the op sequence doesn't end until the se- quence end step is executed, even in the case ofa mishit. fig. 7.3.1 shows the example when the start sequence number is 3, the start sub-sequence number is 3, and the configuration is like fig. 7.1.3. there are two hit entries, hit entry a and hit entry b. the ho_ pin and po_ pin are low level to indicate multi-hits before the op sequence execution. the start sequence number and the start sub-sequence number are set to the op sequence pointer and the op sub- sequence pointer respectively at the sequence pointer reset execution. there is no need to execute the sequence pointer reset just before the op sequence start. for ex- ample, if the sequence pointer reset was executed before the ip sequence, not only the ip start sequence number but also the op start sequence number and the op start sub- sequence number are set at that time. as a result, the op
7-9 address processor ke5b256b1 *1 if the sequence pointer reset is done before the ip sequence start,there is no need to do the sequence pointer reset before the op sequence. *2 the a cannel is selected at the sequence pointer reset, the start sequence number 3 and the start sub sequence number 3 are recognized by opns signal. both start numbers are stored in the opn <2:0> and opns <2:0> of the cntlh register respectively. *3 when oe_is high, output is high impedance. *4 when the cntlh register busy bit = " 1 " *5 when the cntlh register busy bit = " 0 " fig. 7.3.1 timingexample of op sequence *1 *2 opns=1 (a chnnel) . . . hstat hha memhha memhha memhha hha memhha cmp2 segment 0 segment 2 segment 0 segment 2 hit entry a hit entry b *3 *4 *5 ipbusy_/opact_ po_ ho_ od<31:0> oe_ rd_ opch ,opns sqrst_
7-10 address processor ke5b256b1 sequence can be started continuously after the ip sequence end, when the search result is output after the ip sequence. the op sequence takes place as the op sequence pointer or the op sub-sequence pointer is incremented and data is output according to the definition in the aoc register or the aosc register. the first rd_ pulse starts the op sequencer, and the ipbusy_/opact_ changes to low level to indicate that the op sequence is starting. (when the sp/tp_ is low , the device enters the op mode at this time.) the contents of the hstat register is output to the od bus by this pulse and the op sequence pointer is incremented. the op sub- sequence starts with the second rd_ pulse and the entry address of hit entry a is output. segment 0 of the hit entry a is output by the third rd_ pulse. segment 2 of the hit entry a is output by the fourth rd_ pulse, and the output for the hit entry a is ended. the signal of the po_ pin goes high level at this time and it indicates that one hit entry is remaining in the cam table. the entry address of the hit entry b is output by the fifth rd_ pulse and segment 0 of the entry is output by the sixth rd_ pulse. segment 2 of the hit entry b is output by the seventh rd_ pulse and the output for the hit entry b is ended. the signal of the ho_ pin goes high level at this time and it indicates that no hit entry is remaining in the cam table. the op sub-sequence is ended at this time and the sub-sequence pointer is stopped and the control re- turns to the op sequence. the search key data stored in the cmp2 registers output by the eighth rd_ pulse. in this cycle, the op sequence pointer is stopped, the op se- quence ends, and the ipbusy_/opact_ goes high level. the timing of changing the ipbusy_/opact_ at the se- quence end can be set in the following two ways: (1) triggered by the first edge (falling edge) of the rd_ pulse (2) triggered by the second edge (rising edge) of the rd_ pulse if (1) is selected, the timing of changing the ipbusy_/ opact_ is unified to the first edge (falling edge) of the rd_ pulse at sequence start and sequence end, so the tim- ing to monitor the ipbusy_/opact_ is easy to design. however, the op sequence has not completely ended at the timing when the ipbusy_/opact_ goes high. it indi- cates that the op sequence will be ended at this cycle. when the "all output" is set and there are multi-hits, it sometimes can't be known how many times the rd_ pulse will be given. when the ipbusy_/opact_ is monitored to determine if a further pulse should be given or not, more efficient timing can be designed because using (1) allows the timing to be determined earlier. if (2) is selected, the ipbusy_/opact_ goes high level when the op sequence is completely ended. method (2) is recommended when the ipbusy_/opact_ signal is used to control other signal generation. the busy bit of the cntl register selects which timing is being used. method (1) is selected when the bit is set to "1" and (2) is selected when "1". the setting of the bit is common for ipbusy_/opact_ and the opbusy_/ ipact_. suspension and resumption of the op sequence after the op sequence ends, as described before, the op sequence pointer and the op sub-sequence pointer are stopped and rd_ pulses are ignored. the sequence pointer reset must be executed to start the op sequence again. the sequence pointer reset should be executed to suspend the op sequence. the rule of recovery time (min. 20 ns) must be kept to avoid overlapping the rd_ pulse and the ssqrst_ pulse (or the ce_ pulse of the ssqrst_ com- mand). when the sp/tp_ is pulled down and the internal arbitra-
7-11 address processor ke5b256b1 tion is used, this is the case when the timing rule described above can't be kept because the rd_ signal and the ce_ signal are unsynchronized. in this case, the cpu interrupt by the swcpup_im command is recommended. the op sequence will be suspended in the cycle of the next rd_ pulse. if the rd_ pulse is not given for some reason, the cpu interrupt is not recognized and not executed. in this situation, the op sequence should be suspended by the se- quence pointer reset. hha automatic output when the hha automatic output, an option of the ip se- quence, is enabled, the content of the hha register is out- put to the od<31:0> synchronized with the wr pulse. see chapter 6.5 for the settings and the behavior of the hha automatic output. the output data on the od<31:0> bus will be changed to the data set in the op sequence configuration, once the op sequence is started by the rd_ pulse.
8-1 address processor ke5b256b1 8. cpu port 8.1 access to registers register and command all operations through the cpu port are executed as read/ write operations from/to the registers. the desired register should be indicated by the register address add<7:0> in order to access the register through the cpu port. read/ write operation is executed by the low pulse of ce_ . write operation is executed when input to the r/w_ is low and read operation is done when input to the r/w_ is high. commands are executed by the write operation of the op-code to the com register (address 00h). device select and broadcast there are two methods of accessing registers, including command execution. these are the device select method and the broadcast method. the settings as the table configuration or ip/op sequence configuration must be common to all devices in a cascaded system. all devices in a cascaded system should be ac- cessed when writing such information. the method that the host processor accesses to all devices in a cascaded system at the same time is called the broadcast method. if there are hit entries and/or empty entries in plural de- vices, hit information and empty information are trans- ferred from the upper device to the lower device, and the priorities are controlled between the devices. when user accesses to the hha/hea register or the memhha/ memhea register is executed in the broadcast method, the device being accessed is automatically determined by the priority control. the host processor doesn't need to se- lect the device and doesn't need to know which device has the cam table or the register to be accessed. only the lowest device (the last device) can know the sta- tus of all devices in a cascaded system. the last device is automatically selected when the hstat register, which has hit status, or the estat register, which has empty sta- tus, is accessed. a command is issued in the broadcast method at the same time it is issued to all devices. selecting a device is needed to write different data to each device when the host processor writes entry data to the cam table. the method that the host processor accesses to a selecting device is called the device select method. some commands, for example the restore command, need to be used in the device select method. the com- mands to be used in the device select method are shown in table 12.2 of chapter 12, and the registers to be used in the device select method are shown in table 13.4 of chapter 13. the hha/hea register and the memhha/ memhea register can be accessed in the device select method also and the host processor can access the informa- tion of each device. the broadcast method and the device select method is se- lected with the devsel register. the br of the devsel register must be set to "1" to access the broadcast method. the br of the devsel register must be set to "0" and the ds<4:0> of the devsel register must be set to the de- vice id to select and access the device select method. the write operation to the devsel register is executed for all devices, so that the same device id is written to ds<4:0> of all devices. after setting the br to "0," access is ex- ecuted to only the device which has the same device id in both the devid register and the devsel register. the devsel register is always written in the broadcast method. some registers, for example registers for configu- ration, are always written in the broadcast method apart from the devsel register. the last device in a cascaded
8-2 address processor ke5b256b1 system outputs data when such a type of register is read in the broadcast method. see table 13.4 of chapter 13 in de- tail. 8.2 basic operation through cpu port basic operations through the cpu port by accessing the registers in the broadcast method or the device select method, are explained below. device id entry (in a cascaded system) it is necessary to define the device id in the devid regis- ter in order to identify each device in the operation of a cascaded system. refer to section 9.1 for the procedure of the devid definition. basic settings of a device are written to the cntl register. basic settings are for example endian, the polarity of the wr pulse, and the ip/op channel selection method. the contents of cntl register are important data for basic set- tings of a device, the cntl register must be set after de- vice reset (and after device id entry in a cascaded system). the cntl register of all devices are written in the case ofthe device select method, because the contents of the cntl register must be identical for all devices. the cntl register must be written in the situation where there is no access from other ports (cpu mode in the case ofsp/ tp_ = low). cam table definition the cam table definition (table configuration) is ex- ecuted through the cpu port. detailed procedure is shown in section 5.2. tc data is written in the tc sub mode by using the ar and the memar registers. tc configuration must be done for all cam words of all devices. ip sequence configuration and op sequence configu- ration ip sequence configuration and op sequence configuration are done by setting the cut register, the ss register, the cs register, the mask register, the aoc register, and the aosc register. these registers have the 2 channel struc- ture as described in chapter 6 and chapter 7. the registers of the inactive channel are accessed through the cpu port, with special attention paid to which channel can be read/ written. if the active channel selection method of the cntl regis- ter is set to "hardware channel selection," the data which is written to the active channel selection bits (ia<2:0>, oa<2:0>) of the cntl register is ignored. note that in- puts to the ipch pin and the opch pin are registered at the timing of the sequence pointer reset and the active channels are determined. cam table entry and maintenance the read/write operation to the cam table is executed by using the memar register, the memhha register and the memhea register. table operations such as purge, append, and stamp can be executed by using commands for table maintenance. the commands for table mainte- nance are described in section 8.7. all registers can be accessed through the cpu port. the conditions for access to the registers are shown in table 13.4 of chapter 13. all commands are executed by the write operation to the com register. see chapter 12 for the command list. 8.3 search operation through cpu port search operations are mainly executed through the input port. the search operation through the cpu port can be executed by using the srch command or the srch2 command. these commands perform only the search op-
8-3 address processor ke5b256b1 table 8.3.1 registers needed for search commands through the cpu port eration and have no automatic sequence capability, unlike the ip search operation. one search operation is executed per srch/srch2 com- mand. the required data/conditions must be set prior to issuing an srch/srch2 command. the 32-bit key data used in the search is stored to the cpuinp register. the 32-bit mask data is stored to the cpumask register. the segment number to be searched, the search head and the flag (whether or not the access bit is set) are stored to the cpusrs register. the cpuinp2, the cpumask2 and the cpusrs2 are used in the case ofthe srch2 com- mand. the registers which must be set prior to the srch/ srch2 command are shown in table 8.3.1. the registers for the srch command and the registers for the srch2 command are independent. the detailed description for registers are shown in chapter 13. after setting the above registers, a search operation is ex- ecuted when the srch/srch2 command is issued. the search results are stored to registers and output to the flag output pin. 80h, 81h 82h, 83h 84h 86h, 87h 88h, 89h 8ah (1) srch command ( op-code 60h ) register name register name (2) srch2 command ( op-code 76h ) cpuinp(l, h) re g ister cpuinp2(l, h) register cpumask(l, h) re g ister cpumask2(l, h) register cpusrs register cpusrs2 register address address data to set data to set search key data search key data search mask data search mask data search se g ment nunber search se g ment number access bit set on/off access bit set on/off search head/and search search head/and search
8-4 address processor ke5b256b1 table 8.4.1 registers for search result output 8.4 search result output from cpu port the results of an ip search or a cpu search are reflected to the registers and the flag output pins described in chapter 6. these registers, except for the sh register, can be read using the op sequence described in chapter 7. these reg- isters can also be read from the cpu port. the registers to read the results of a search are shown in table 8.4.1. the hstat register stores device hit, device multi-hit, system hit, system multi-hit , etc. device hit/device multi- hit of each device are read in the device select method, system hit/system multi-hit of a whole system are read in the broadcast method, or read in the last device in the device select method. the sh register should be read in the device select method because the sh register of a device stores the ip sequence results of the device. the memhha register must be accessed after the search operation is completed so that the destruction of the cam table is avoided, as described in chapter 4 and chapter 6. the memhha can be accessed in the cpu mode when the sp/tp_ pin is pulled down (internal arbitration). when the sp/tp_ pin is pulled up (external arbitration), the memhha register must be accessed after the search cycle (input port cycle or cpu port cycle of srch/srch2 command) is finished. the ac timing of wr to ce_ and ce_ to ce_ (ce_ cycle) described in chapter 14 must be kept to access the memhha register correctly. the ac- cess to the cmp is same as the access to the memhha. the hstat register, the hha register and the sh register can be read in the modes other than the cpu mode when the sp/tp_ pin is pulled down (internal arbitration). but search key data used in each step of the ip sequence hit, multi-hit etc. of each device and cascaded system highest hit address entry data pointed by the cam address in the hha register hit in each step of the ip sequence register name cmp register (cmp0l/cmp0h- cmp7l/cmp7h) hstat register hha(h,l)register memhha register sh register data to set address a0h, afh 90h 94h, 95h 0eh 98h
8-5 address processor ke5b256b1 the ac timing of wr to ce_ and ce_ to ce_ (ce_ cycle) must be kept to read out the search results. hit information propagates with some delay from the up- per device to the lower device in a cascaded system. it takes some time to determine the search results because of propagation delay. timing design needs to consider the number of devices. see section 9.6 for timing consider- ation in a cascaded system. 8.5 hha/hea register operation hha register the hha register is used as the pointer to hit entry, and the hit entries can be accessed in order of hit priority. the entry address of the highest hit priority is set to the hha register when the search operation (input port cycle or cpu port cycle of srch/srch2 command) is completed or the gen_hit command is executed. the pointer to hit entry is forwarded and the hha register stores the entry address of the next hit priority when the nxt_hh command is executed. all hit entry addresses of all devices in a system can be read by repeating this proce- dure. the segment data of the entry indicated by the hha register can be obtained by access to the memhha regis- ter. the hha register has the hv flag (highest hitaaddress validitf flag). the address indicated by the hha register is valid if the hv flag is "1." the address indicated by the hha register is not valid if the hv flag is "0" and it indi- cates that there is no hit entry or all hit entry addresses have been read. the pointer to hit entry is rewound when the gen_hit command is executed. the entry address of the highest hit priority is set to the hha register by this command. search result output change by the hha register operation the output of the ho_ pin and the po_ pin and the data of the hstat can be changed by the operation, which changes the data of the hha register. ho_ pin the address indicated by the hha is forwarded by the nxt_hh command, and the output of the ho_ pin be- comes high when no hit entry exists in the lower address area than the address indicated by the hha address. the output of the ho_ pin of the lowest device (last device) becomes high in the case ofa cascaded system. the output of the pin returns to where it was before when the address indicated by the hha register is rewound to the highest priority hit address by the gen_hit command. po_ pin the address indicated by the hha is forwarded by the nxt_hh command, and the output of the po_ pin be- comes high when one hit entry exists in the lower address area than the address indicated by the hha address. the output of the po_ pin of the lowest device (last device) becomes high in the case ofa cascaded system. the output of the pin returns to the previous level when the address indicated by the hha register is rewound to the highest priority hit address by the gen_hit command. hstat register the data of the hstat register is changed as the output of the ho_ pin and the po_ pin with the changes of the hha register data. hea register the hea register is used as the pointer to empty entry, and the empty entries can be accessed in order of empty prior-
8-6 address processor ke5b256b1 ity. the entry address of the highest empty priority is set to the hea register when the gen_fl command is executed. the pointer to empty entry is forwarded and the hea reg- ister stores the entry address of the next empty priority when the nxt_he command is executed. all empty entry addresses of all devices in a system can be read by repeat- ing this procedure. the segment data of the entry indicated by the hea register can be accessed by access to the memhea register. the hea register has the ev flag (highest empty address validityfflag). the address indicated by the hea register is valid if the ev flag is "1." the address indicated by the hea register is not valid if the ev flag is "0," and it indi- cates that there is no empty entry or all empty entry ad- dresses have been read. the pointer to empty entry is rewound when the gen_fl command is executed. the entry address of the highest empty priority is set to the hea register by this command. the key data used in the search operation is copied into the entry indicated by the hea register automatically after the search operation (see section 8.7: append commands) therefore, the segment data of entry indicated by the hea register is always renewed with the search operation. if the hea register is not renewed after adding the segment data into the entry indicated by the hea register, content of the added table is changed by the next search operation. if the user adds the segment data into the entry indicated by the hea register, the hea register has to be renewed by the gen_fl or nxt_he command. empty output change by the hea register operation the output of the flo_ pin and the data of the estat can be changed by the operation which changes the data of the hea register. flo_ pin the address indicated by the hea is forwarded by the nxt_he command. and the output of the flo_ pin be- comes high when no empty entry exists in the lower ad- dress area than the address indicated by the hea address. the output of the flo_ pin of the lowest device (last de- vice) becomes high in the case ofa cascaded system. the output of the pin returns to the previous level when the address indicated by the hea register is rewound to the highest priority empty address by the gen_fl command. estat register the data of the estat register is changed as the output of the flo_ pin interacts with the changes of the hea regis- ter data. 8.6 automatic increment function automatic increment of hha and hea registers automatic increment of the hha register and the hea register is implemented. this function enables the hha/ hea register to be incremented without the nxt_hh/ nxt_he command. it is easy to read out entry addresses. automatic increment of the hha register is enabled by setting the hhi in the cpuhs register to "1." if the auto- matic increment of the hha register is enabled, the data in the hha register is shifted to the entry address with the next hit priority after the hhal register, which is the lower 16-bit register of the hha register and is accessed. therefore, in the next read operation of the hha register, the entry of the next hit entry is output. this function en- ables the user to read all hit entry addresses by only read- ing the hha register repeatedly without executing the nxt_hha command.
8-7 address processor ke5b256b1 automatic increment of the hea register is enabled by setting the hei in the cpuhs register to "1." if the auto- matic increment of the hea register is enabled, the data in the hea register is shifted to the entry address with the next hit priority after the heal register, which is the lower 16-bit register of the hea register, and is accessed. therefore, in the next read operation of the hea register, the entry of the next hit entry is output. this function en- ables the user to read all empty entry addresses by only reading the hea register repeatedly without executing the nxt_hea command. automatic increment of hha and hea registers by stamp commands stamp commands execute maskable writing, which is called stamping, to the segment data of the specified entry. details of the stamp commands are shown in section 8.7. the stamp commands also have the automatic increment capability of the hha and hea registers. if the shi in the cpuhs register is set to "1," the auto- matic increment of the hha register at the execution of the stmp_hh, stmp2_hh commands (stamping to hit entry) is enabled. if this function is set, the data in the hha register is automatically shifted to the entry address with the next hit priority after execution of the stmp_hh, stmp2_hh command. it enables the user to stamp hit en- tries successively by only repeating the stmp_hh, stmp2_hh command. if the sei in the cpuhs register is set to "1," the automatic increment of the hea register at the execution of the stmp_he, stmp2_he commands (stamping to empty entry) is enabled. if this function is set, the data in the hea register is automatically shifted to the entry address with the next empty priority after execution of the stmp_he, stmp2_he command. it enables the user to stamp empty entries successively by only repeating the stmp_he, stmp2_he command. automatic increment of memhha and memhea register automatic increment capability is also provided for access to the segment data of the cam table through the memhha and memhea registers. the segment auto- matic increment, the entry automatic increment, and the segment and entry automatic increment are available. ac- cess with no automatic increment also can be used. the access mode to memhha, and memhea is defined by hm<1:0>, em<1:0> in the cpuhs register. there are some cases, that the hha register or the hea register is incremented doubly if this function and the automatic in- crement of the hha,hea register are used together. note the setting of hm<1:0>, em<1:0>, shi, and sei in the cpuhs register to avoid the double increment. no automatic increment this is the access mode with no increment. this access mode is selected when the hm<1:0> or em<1:0> is set to "00." the segment number to be accessed in the entry must be specified by the fixed segment number (hfs<2:0> or efs<2:0>) in the cpuhs register. segment automatic increment this is the access mode to access a hit entry or an empty entry in the order of the segment number . this access mode is selected when the hm<1:0> or em<1:0> is set to "01." in this access mode, the segment counter, which is the ring counter of modulo "segment number of one entry -1," is used as the pointer to the segment data to access. the cor- rect segment number must be written to the ww<2:0> be- cause the modulo of the ring counter is determined by the ww<2:0> .
8-8 address processor ke5b256b1 there are two segment counters, one for hit entry and one for empty entry. the fixed segment number (hfs<2:0> or efs<2:0>) in the cpuhs register is ignored when this ac- cess mode is selected. in the first access to the memhha or memhea regis- ters, the data of the head segment (segment no. 0) is read/ written. after the first access (two cycle read/write when the endian is on, one cycle read/write when the endian is off) is executed, the corresponding counter is incremented, and points to the next segment. after the last segment of an entry is accessed, the segment counter value goes to "0" and the head segment of the entry is pointed. all segments in an entry can be read/written consecutively by using this access mode. the hs<2:0> and es<2:0> in the cpuhs register stores the segment counter value. the segment number to access next can be known by reading these bits. these bits cannot be changed by writing. entry automatic increment this is the access mode where the segment number to be accessed is fixed, and the data of hit entry or empty entry is accessed in order of priority. this access mode is selected when the hm<1:0> or em<1:0> is set to "10." the segment number to be accessed is specified by the hfs<2:0> or efs<2:0> in the cpuhs register. in this mode, the value of the segment counter is not used. after the access to the memhha register or the memhea register (two cycle read/write when the endian is on, one cycle read/write when the endian is off) is ex- ecuted, the hha register or the hea register is incremented and points to the next priority hit entry or empty entry. segment and entry automatic increment this access mode is the combination of the segment auto- matic increment and the entry automatic increment. all segments of all hit entries or empty entries can be ac- cessed. this access mode is selected when the hm<1:0> or em<1:0> is set to "11." segment increment in an entry is the same as the segment automatic increment according to the segment counter. the data of the entry indicated by the hha register or the hea register is accessed from the head segment in order of segment number. the hha register or the hea register is incremented when the last segment of the entry is ac- cessed. the hha register or the hea register stores the address of the next hit priority or the next empty priority and the segment counter is reset to "0" at that time. all data of the hit entry or all empty entries can be read/written con- secutively by the same procedure. reset condition of segment counter the initial value of the segment counter is "0" after the device reset. there is another case when the segment counter is reset. table 8.6.1 shows the reset condition of the segment counter and also shows the reset condition of the endian toggle. the segment counter for the memhha register/ memhea register is reset when the data of the hha reg- ister/hea register is changed. the segment counters are reset when the cpuhsl register is written, because the increment mode is changed. endian toggle is reset when one or both of the segment counters are reset because the segment to be accessed is changed. 8.7 table maintenance some useful commands are provided for table mainte- nance. the combination of these commands and the access through the memar, memhha, memhea register
8-9 address processor ke5b256b1 *1 when the hhi bit in the cpuhs register is "1" *2 when the heibit in the cpuhs register is "1" *3 when the shi bit in the cpuhs register is "1" *4 when the sei bit in the cpuhs register is "1" table 8.6.1 reset conditions for segment counter and endian toggle operation s eg me nt cou nter for memhha access s eg me nt cou nter for memhea access endian tog g le device reset w rite to ar register ip search srch command srch2 command nx t hh c om mand nxt he command gen fl command nxt hit command append nhe command hha register acces s w hen hha register automatic increment is enable *1 hea register access w hen hea re gis ter automatic increment is enable *1 stmp_hh command w hen hha register automatic increment is enable *3 s tmp2 _hh c om mand w hen hha register automatic increment is enable *3 stmp_he command w hen hea re gis ter automatic increment is enable *4 stmp2_he command w hen hea re gis ter automatic increment is enable *4 w rite cpuhs l reg iste r : reset : not reset
8-10 address processor ke5b256b1 fig. 8.7.1 table maintenance makes the table maintenance easy. the description of the commands is given by using the ex- ample of the cam table shown in fig. 8.7.1. fig. 8.7.1. shows an example which is configured for four segments per entry. valid data is written from entry num- ber 0 to entry number 5, and entry number 6 is empty. the access bits of entry numbers 3 and 5 are set with the result of several searches. entry numbers 1 and 3 are hit entries because the last search and the hit flags of these hit entries are set. the hha register stores "4h," the entry address of entry number 1 which is the highest priority hit entry. the hea register stores "18h," the entry address of entry number 6, which is the highest priority empty entry. the description of how this cam table changes when each command is executed in this situation is shown. purge commands purge commands make desired entries empty. the empty bit of the head segment of the specified entry is set to "1" when purge commands are executed. by this action, the entry becomes an empty entry and excluded from search. there are seven purge commands as follows: prg_al prg_nac prg_ac prg_nacwh prg_acwh prg_hh prg_ar the commands except the prg_hh, prg_ar can purge more than one entry complying with the status of cam se g ment number entry number 0 oh 4h 8h ch 10h 14h 18h 1h 5h 9h dh 11h 15h 19h 2h 6h ah eh 12h 16h 1ah 3h 7h bh fh 13h 17h 1bh 0123 1 2 3 4 5 6 cam address 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 1 0 1 0 empty bit hit flag access bit hha = 4h(entry number 1) hea = 18h(entry number 6)
8-11 address processor ke5b256b1 table. the prg_hh and prg_ar commands can purge only one entry. the prg_al command makes all entries in the device empty. the prg_nac command makes all entries whose access bits are "0," empty. in the table shown in fig. 8.7.1, entry numbers 0, 1, 2, and 4 are purged when the prg_nac command is executed. (entry number 6 is already empty) the prg_ac command makes all entries whose access bits are "1" empty. in the table shown in fig. 8.7.1, entry numbers 3 and 5 are the entries to be purged when the prg_ac command is executed. all access bits are cleared to "0" but all hit flags are not changed when the prg_al, the prg_nac or the prg_ac commands are executed. when all access bits are desired to clear without purging a entry, the rst_ac command is used. the prg_nacwh stands for prg_nac with hit, so the entry whose access bit is "0" and hit flag is "1" is purged by the prg_nacwh command. the entry number 1 is purged when the prg_nacwh command is executed as per the table in fig. 8.7.1. the prg_acwh stands for prg_ac with hit, so the entry whose access bit is "1" and hit flag is "1" is purged by the prg_acwh command. the entry number 3 is purged when the prg_acwh command is executed to the table in fig. 8.7.1. not only the status of the access bit but also the status of the hit flag of an entry determine whether the entry is purged or not, when the prgnac_wh command or the prgac_wh command is executed. the specified entries can be protected, by a search operation before the prg_acwh or the prg_nacwh commands. the search operation limits the entries to be purged. the prg_nacwh and prg_acwh commands clear the access bits of the entries whose hit flags are "1" to "0." the access bits of all hit entries can be cleared by the rst_acwh command. the prg_hh command purges the entry which is indi- cated by the hha register. in the table of fig. 8.7.1, the entry number 1 is purged. the entry of the highest hit pri- ority of all devices is purged when this command is ex- ecuted in the broadcast method. the entry of the highest hit priority of the device selected is purged when this com- mand is executed in the device select method. the access bit of the entry purged by the prg_hh command is cleared. the prg_ar command purges the segment indicated by the ar register. the entry address (the cam address of the head segment) of an entry must be set to the ar regis- ter when the prg_ar command is used for purging the entry. the access bit of the entry purged by the prg_ar command is cleared. this command can be executed in the device select method. the empty bits of the purged entries are set to "1" when a purge command is executed, but the hea register doesn't change at that time. therefore the gen_fl command must be executed after the purge command. wrong results may appear if the gen_hit command is not executed af- ter the purge command. the empty bits of all entries are recognized again by the gen_fl command, then the hea register stores the correct address, the estat regis- ter stores the correct value, and the flo_ pin outputs the correct status at the same time. for example, when the prg_hh command is executed for the table in fig. 8.7.1, the entry number 1 becomes empty. but the hha register still stores "4h," the entry address of entry number 1, and the hea register still stores "18h," the entry address of entry number 6. the hha reg- ister renews to "ch" when the gen_hit command is executed. the hea register renews to "4h" when the hea command is executed.
8-12 address processor ke5b256b1 restore the restore command is provided to make an empty entry valid (not empty). this command is useful when user restores a specific entry among those entries which have been made empty by the purge commands. the empty bit of the head segment of the specified entry is set to "0." the restored entry is counted among valid entries for search operations after that. the entry to be restored is determined by the ar register. when the restore command is executed, the entry ad- dress (the head segment address) of the desired entry must be stored in the ar register. the hea register doesn't change by the execution of the restore command, so the gen_fl command must be executed to renew the hea register. the restore command can be executed only in the device select mode. nxt_he the nxt_he command is provided to continue the hea register. the nxt_he command makes the hea register store the entry address of the next priority empty entry. gen_fl the gen_fl command is provided to renew the hea register. the hea register stores the entry address of the highest priority empty entry when this command is ex- ecuted. the change of empty bits must be reflected to the hea register by executing this command after operations for changing empty bits, such as the addition of an entry, and the purge commands, are executed. if this command is not executed, added segment data is possible to destroy (see this section: append). therefore, after the following op- erations, this command must be executed. ? table configuration ? entry data registration using the memhea or memar register. ? execution append command ? execution purge command ? execution stamp command to the empty entry ? execution restore command nxt_hh the nxt_hh command is provided to continue the hha register. the nxt_hh command makes the hha register store the entry address of the next priority hit entry. for example, if the nxt_hh command is executed to the table in fig. 8.7.1, then the hha register stores "ch," the head segment address of the next priority hit entry. gen_hit the gen_hit command is provided to renew the hha register. the hha register stores the entry address of the highest priority hit entry when this command is executed. the empty bit of each entry is evaluated when this com- mand is executed. if hit entries are purged, the purged hit entries become no-hit entries when this command is ex- ecuted. the gen_hit command can be executed to re- wind the hha register, which is forwarded by the nxt_hh command or the automatic increment of the hha register. append commands the append commands are provided to write the key data used in the search to the cam table. this command is used to append the key data which is not hit in the search. there are the append command and the append_nhe com- mand. append the key data is automatically stored to the empty entry in-
8-13 address processor ke5b256b1 dicated by the hea register when the search operation is performed. the segment number of the stored key data is the same as the segment number to be searched. at the end of the search operation, a series of the key data is stored to the entry pointed by the hea register. data is not written to the segments which are not searched. the bits masked by the mask register or the cpumask register are not written and the data before search operation is kept. in example fig. 8.7.1, the key data in the search operation is copied to the entry number 6. the key data is copied to cam address 18h when the segment number 0 is searched and the key data is copied to cam address 1ah when the segment number 2 is searched. the key data is copied from the search operation but the empty bit of that entry is still "1." the entry storing the copied data is not valid at that time. if the append com- mand is executed in this situation, the empty bit of the entry is set to "0" and the entry becomes valid for search operation. this written procedure is called "append." the entry address is indicated by the hea register, and the appended entry can be confirmed by reading the hea reg- ister. segment data of the entry can be changed and added by writing to the memhea register after setting the seg- ment number in the cpuhs register. if there is no entry at search operation, the key data is not copied and the append command is invalid. after the append command is issued, the success of the append command can be confirmed by reading the as bit (ap- pend result flag) . the hea register is not changed when the append com- mand is executed. the key data in the next search will be copied to the appended entry if no operation is executed after the append command. to avoid this, the hea reg- ister must be renewed by the gen_fl command or the hea register is incremented by the nxt_he command. append_nhe the append_nhe command is the combined command of the append command and the nxt_he command. the hea register is automatically incremented at the end of the append operation. the execution of the gen_fl and the nxt_he is not needed after the command. re- ducing the operational cycles may be possible. stamp the stamp command is the maskable write function by bit unit. it can be useful to register hit time to the hit entry, the data to be written to the cpuinp register, and the mask data to the cpumask register. the data is not writ- ten to the masked bits and previous value is kept. the cpuinp register and the cpumask register are common registers for search operation and stamp opera- tion. there is another set of these registers, the cpuinp2 register and the cpumask2 register, so that the key data/ mask data of search operation and the stamp data/ mask data of stamp operation can be set separately. when the stamp command is executed, the empty bit of the segment which is stamped is cleared to "0." if the com- mand is executed to the head segment of an entry, it has the same effect as when the entry is added. in this case, the gen_fl command should be executed to renew the hea register. there are several commands in the stamp command group, as shown below. stmp_ar, stmp2_ar command these commands stamp on the segment indicated by the ar register. the stmp_ar command uses the data of the cpuinp register and the cpumask register. the stmp2_ar command uses the data of the cpuinp2 reg-
8-14 address processor ke5b256b1 ister and the cpumask2 register. stmp_hh, stmp2_hh command these commands stamp on the entry indicated by the hha register. the stmp_hh command uses the data of the cpuinp register and the cpumask register. the stmp2_hh command uses the data of the cpuinp2 reg- ister and the cpumask2 register. the methods to indicate the segment to be stamped are dif- ferent for both commands. the hfs<2:0> bits of the cpuhs register are used to specify the segment for the stmp_hh command. the memhha automatic incre- ment method bits (hm<1:0>) of the cpuhs register must be set to "00" (no increment ). the cg<2:0> bits of the cpuhs register are used to specify the segment for the stmp2_hh command. in this case, the memhha auto- matic increment method bits (hm<1:0>) of the cpuhs register do not need to be set to "00" (no increment). the stmp_hh and the stmp2_hh commands don't sup- port the segment automatic increment. if these commands are executed for more than one segment, the designation of the segment by the hfs<2:0> or the cg<2:0> bits is needed for each command execution. the automatic incre- ment described in section 8.6 can be used if these com- mands are executed for more than one entry. stmp_he, stmp2_he command these commands stamp on the entry indicated by the hea register. the stmp_he command uses the data of the cpuinp register and the cpumask register. the stmp2_he command uses the data of the cpuinp2 reg- ister and the cpumask2 register. the methods to indicate the segment to be stamped are dif- ferent for both the stmp_hh and the stmp2_hh com- mands. the efs<2:0> bits of the cpuhs register are used to specify the segment for the stmp_he command. the memhea automatic increment method bits (em<1:0>) of the cpuhs register must be set to "00" (no increment ). the cg<2:0> bits of the cpuhs register are used to specify the segment for the stmp2_he command. in this case, the memhea automatic increment method bits (em<1:0>) of the cpuhs register do not need to be set to "00" (no increment). the stmp_he and the stmp2_he commands don't sup- port the segment automatic increment. if these commands are executed for more than one segment, the designation of the segment by the efs<2:0> or the cg<2:0> bits is needed for each command execution. the automatic incre- ment described in section 8.6 can be used if these com- mands are executed for more than one entry. automatic swiop the append commands (append, append_nhe com- mand) and stamp commands (stmp_ar, stmp_hh, stmp_he, stmp2_ar, stmp2_hh, stmp2_he com- mand) have the function of automatic swiop, as de- scribed in chapter 4. using this function, the mode can be switched to the iop mode without issuing the swiop command, and processing time can be reduced (when the sp/tp_ is pulled down and the internal arbitration is used). this function is not needed when the sp/tp_ is pulled up and the external arbitration is used, because the swiop itself is not needed in the case ofthe external arbitration. if the apm bit (automatic swiop for append command enable flag) in the cpuhs register is set to "1," the mode transition into the iop mode occurs immediately after the execution of the append or append_nhe commands. if the apm in the cpuhs register is set to "0," the auto- matic swiop is disabled and the mode transition does not occur. if the stm bit (automatic swiop for stamp command en-
8-15 address processor ke5b256b1 able flag) in the cpuhs register is set to "1," the mode transition into the iop mode occurs immediately after the execution of the stmp_ar stmp_hh, or stmp_he command. if the stm in the cpuhs register is set to "0," the automatic swiop is disabled, and the mode transition does not occur. if the append command is executed with automatic swiop enable, the mode is switched to the iop mode without renewing the hea register. please be aware that the device may not work correctly after this operation. (it is recommended to use the append_nhe command if appending an entry when automatic swiop enable is ex- ecuted.) if the stmp_he command is executed with automatic swiop enable, the mode is also switched to the iop mode without renewing the hea register. it is important to rec- ognize that the device may not work correctly after this operation. (it is recommended to use the stmp_he com- mand with the hea register automatic increment enable if the stmp_he command with automatic swiop enable is executed.) when a command with automatic swiop enable is ex- ecuted, the mode is changed and the ipbusy_/opact_, opbusy_/ipact_ are changed as the mode is changing. the ipbusy_/opact_, opbusy_/ipact_ output will be changed from the rising edge of the ce_ signal. see chapter 14 (ac characteristics) in detail.
9-1 address processor ke5b256b1 9. cascading 9.1 device id registration the ap can be cascaded to a maximum of 32 devices. a cascaded system can be treated as one device which has a larger table size. it is necessary to define the device id in the devid register in order to identify each device in the operation of a cascaded system. the procedure for registra- tion of the device id is shown in fig. 9.1.1. in order to set the device id, the devices in a cascaded system must be moved into the devid sub-mode by the str_devid command. the str_devid command en- ables be the user to apply read/write operations to the devid register of the highest (top) device in the cascaded system. the device id is set to the di<4:0> of the register. after that, the device id of the next device can be set by the nxt_pr command. the registration should be re- peated down the chain until each device is given a unique device id by repeating these operations. if the str_devid command is executed among these opera- tions, it returns to the status where by the devid of the highest (top) device can be read/written. the device id must be a continuous number starting from the top device. the ld in the last device devid register must be set to "1." this bit indicates that the device has the lowest priority , and it is used to control the data outputs. the ld bits of all devices except the last device must be set to "0." after the devid registers of all devices are set, the devices should be moved into the normal operation mode from the devid sub-mode by executing the end_devid com- mand. the devices must leave the devid sub-mode after all device ids are set, because the operations like table configuration, or search can't be executed correctly in the devid sub-mode. about 1 us waiting time is recom- mended to ensure that the pi_ and po_ pins become stable. the device ids of all devices are initialized to the same value "00000" after device reset. the operations described above, from the str_devid command to the end_devid command, must be executed after device re- set. if only one device is used, the device id registration is not necessary. don't register the device id in normal operation mode once the device id is set after device reset. 9.2 priority in a cascaded system , the data buses of the input port, the output port and the cpu port must be connected to all devices. as for the input port, the same data is written to all devices through id<31:0> and the same ip sequence is ex- ecuted. as for the output port, the output device is auto- matically determined in a cascaded system. as for the cpu port, the output device is automatically determined in the broadcast method and the device to be written is also auto- matically determined when the memhha or the memhea register is written in the broadcast method. the priorities are used for these controls. there are three priori- ties: hit priority, empty priority and devid priority. prior- ity controls work without adding any external logic, if the hi_, ho_, pi_, po_, fli_, and flo_ are cascade-con- nected so that the priorities can be propagated. (1) hit priority in a cascaded system, the uppermost located device among all devices that have hit entries is defined as having hit pri- ority. in reading out the hha register and the memhha register with the broadcast method, the device which has hit priority outputs the data. hit priority is propagated through the hi_ and ho_ pins. (2) empty priority in a cascaded system, the uppermost located device among all devices that have empty entries is defined as having
9-2 address processor ke5b256b1 fig. 9.1.1 device idregistration * ld bit,msb of devid register,of the last device must be set to " 1 ". * 1 us waiting time must be taken after the end_devid command. 00h 04h 00h 00h 04h 04h 00h 22h 01h 22h 20h 00h m 21h ce_ add<7:0> dat<15:0> write to com register write to com register write to devid register write to devid register write to com register write to devid register write to com register str_devid command nxt_pr command nxt_pr command end_devid command devid sub-mode devid =0 devid =1 devid =2 devid =m cascaded devices 0 0 0 0 0 0 0 0 15 ld di<4:0> 15 0 0 0 0 0 0 1 0 ld di<4:0> 0 0 0 0 0 1 0 1 m (binary) 15 0 ld di<4:0> 15 0 ld di<4:0>
9-3 address processor ke5b256b1 empty priority. in reading out the hea register and the memhea register with the broadcast method, the device which has empty priority outputs the data. empty priority is propagated through the fli_ and flo_ pins. (3) devid priority devid priority specifies which device accepts the device id data in the devid sub-mode. devid priority is propa- gated through the pi_ and po_ pins in the devid sub- mode. however, the pi_ and po_ pins propagate multi-hit information in something other than the devid sub-mode. the device located at the bottom of the cascaded chain must be known in order to perform internal control of the device. the ld bit in the devid register of the bottom device must be set to indicate that it is the "last device." for example, the last device outputs the data of the hstat register when the hstat register is read by the broadcast method, because the last device stores the total hit information of the cascaded system. if there is no device having hit priority, the last device outputs the data of the hha register in the broadcast method. the hv flag of the output data is "0" and that indicates that the hha is invalid. the last device outputs the data when the registers con- taining devices that have the same data, such as the cntl register and the ip/op configuration register, are read by the broadcast method. 9.3 cascade connection the pins must be connected as shown in fig. 9.3.1 (a), (b) when multiple devices are cascaded, up to a maximum of 32 devices. the key data for search operations will be si- multaneously input to all the devices by connecting the id<31:0> of the input port. the od<31:0> of the output port are also connected to each other. the hit priority de- vice or the last device is selected as the output device ac- cording to the output data by internal control. there is no device select method for the input port and the output port. input data for the cpu port will be applied to all the de- vices by connecting the dat<15:0> . at data output, the device selected by the device select method or the device which has priority by the broadcast method is selected as the output device by internal control. if there is no device which has priority, the last device outputs the data. the hi_ and ho_ pins propagate hit priority. the ho_ pin of the upper device and the hi_ pin of the lower device must be connected and the hi_ pin of the top device must be set to the high level. the pi_ and po_ pins propagate signals which show whether the upper devices have multiple hits or not. how- ever, these pins propagate the devid priority as shown in section 9.2 in the devid sub-mode. the pi_ pin of the top device must be set to the high level. the fli_ and flo_ pins propagate empty priority. the flo_ pin of the upper device and the fli_ pin of the lower device must be connected and the fli_ pin of the top de- vice must be set to the low level. the outputs of the opbusy_/ ipact_ pins of all devices are changed at the same cycle because the same sequence is executed for all devices simultaneously in the ip sequence. as for the op sequence, the outputs of the ipbusy_/ opact_ pins of all devices become low at the same cycle in the beginning of the sequence. the timing when the ipbusy_/opact_ of each device becomes high is differ- ent because the output device is changed as the hit priority moves, if there are multi-hits and "all" output is set. the end of the op sequence is the cycle when the ipbusy_/ opact_ of the last device becomes high. so the ipbusy_/opact_ of the last device must be used to monitor the ipbusy_/opact_ signal. the opf bit of the devstat register must be read to confirm the status by reading the register. the sh0_ and sh1_ pins output whether there is a hit or
9-4 address processor ke5b256b1 fig. 9.3.1 cascade connection (a) signals of the input and output port ke5b256b1 gnd wr sh1_ sh0_ ipbusy_/opact_ id<31:0> rd_ oe_ od<31:0> opbusy_/ipact_ fli_ pi_ hi_ flo_ po_ ho_ vdd wr sh1_ sh0_ ipbusy_/opact_ id<31:0> rd_ oe_ od<31:0> opbusy_/ipact_ fli_ pi_ hi_ flo_ po_ ho_ wr sh1_ sh0_ ipbusy_/opact_ id<31:0> rd_ oe_ od<31:0> opbusy_/ipact_ fli_ pi_ hi_ flo_ po_ ho_ flo_ po_ ho_ ke5b256b1 ke5b256b1 ke5b256b1 rd_ oe_ od<31:0> wr id<31:0> ipbusy_/opact_ sh1_ sh0_ vdd vdd note : ho_, po_, flo_, ipbusy_/opact_ of the last device must be monitored as system information.
9-5 address processor ke5b256b1 fig. 9.3.1 cascade connection (cont'd) (b) signals of the cpu port ke5b256b1 gnd ce r/w_ dat<15:>0 add<7:0> ipbusy_/opact_ fli_ pi_ hi_ flo_ po_ ho_ vdd ce r/w_ dat<15:0> add<7:0> ipbusy_/opact_ fli_ pi_ hi_ flo_ po_ ho_ ce r/w_ dat<15:0> add<7:0> ipbusy_/opact_ fli_ pi_ hi_ flo_ po_ ho_ flo_ po_ ho_ ke5b256b1 ke5b256b1 ke5b256b1 opbusy_/ipact_ opbusy_/ipact_ opbusy_/ipact_ ipbusy_/opact_ ce_ r/w_ dat<15:0> add<7:0> note : ho_, po_, flo_, ipbusy_/opact_ of the last device must be monitored as system information.
9-6 address processor ke5b256b1 not at each sequence number, which is defined in the shasgn register in the ip sequence. if the sequence num- ber defined in the shasgn register is set to and search, the result of and search is output. the sh0_ and sh1_ pins are open-drain outputs. if these pins are wired through the cascaded devices, they indicate the sequence hit results as the system status. the cascaded system can be considered as one cam with a larger table capacity after the configuration for all devices done. such system information as hit and empty priority are stored in the hstat and the estat register of the last device. when these registers are read out by the broadcast method, the last device will output the information. 9.4 input port in a cascaded system ip sequence configuration the same ip sequence configuration (search key data for- mat, segment number to be searched, mask setting) is set to all devices of a cascaded system. the data input to id <31:0> of the ip port is formatted according to the con- figuration and used for search operations. the broadcast method is only available when the registers for ip sequence configuration are written and the same data is written to all devices. whether correct data is written to each device or not can be confirmed by reading the registers in the device select method. the last device outputs data if these regis- ters are read in the broadcast method. ip search the data to the input port is simultaneously input to all devices through id<31:0>. all devices execute the same ip sequence when a wr pulse is input. the ho_ pin of the last device outputs the search result whether there is a hit or not, and the po_ pin of the last device outputs whether there are multi-hits or not. the timing when these signals become valid is different ac- cording to the numbers of cascaded devices. refer to sec- tion 9.7 and chapter 14 for the ac characteristics in a cas- caded system. all devices start the ip sequence simulta- neously and end simultaneously. 9.5 output port in a cascaded system the same op sequence configuration is set to all devices of a cascaded system like the ip sequence configuration. the broadcast method is only available when the registers for the op sequence configuration are written. whether cor- rect data is written to each device or not can be confirmed by reading the registers in the device select method. the last device outputs data if these registers are read in the broadcast method. op output the output device is automatically selected with internal control. table 9.5.1 shows which device outputs data in detail. as described in the section 9.3, all devices start the op sequence at the same time but there are some cases that each device ends the op sequence at different time. the last device must be monitored to know the end of the op sequence. this point should be considered when an opera- tion to other ports is executed after the op sequence end. hha automatic output the devices which have a hit output the hha of the device regardless of hit priority when hha automatic output is set in the ip sequence. if more than one device have a hit, col- lisions on the od bus happens. as described in section 6.5, the ip sequence number that hha automatic output is en- abled should be considered carefully to avoid the collisions.
9-7 address processor ke5b256b1 table 9.5.1 data output device in the op sequence 9.6 cpu port in a cascaded system read/write registers read/write operations (including command execution) can be performed by both the broadcast method and the device select method. this selection is defined in the devsel register. the br in the devsel register must be set to "0" when the device select method is selected. the selected device can be speci- fied by the di<4:0> in the devsel register. the br must be set to "1" when the broadcast method is selected. when data is written to a register, one of the following op- erations is executed according to the attribute of the regis- ter: write to all devices simultaneously write to the device which has hit priority write to the device which has empty priority when data is read from a register, one of the following op- erations is executed according to the attribute of the regis- ter: read from the last device read from the device which has hit priority read from the device which has empty priority the device to be accessed is selected automatically by in- ternal control. the device select method is invalid and data is written to all devices when the data is written to the register which must have common data for all devices. some registers must be *1 if the mixed output mode with the hstat register is specified , bits of the hstat register are output from the last device. *2 if the hv bit (hha valid flag) becomes "0" (invalid), output of the hha register is invalid. the hha register outputs invalid data. output register name hit in system no hit in system cmp reg i ster d ev i ce w i t h hi t pr i or i ty l ast d ev i ce hstat reg i ster l as t d ev i ce l as t d ev i ce hha register device with hit priority last device *2 memhha reg i ster d ev i ce w i t h hi t pr i or i ty l ast d ev i ce *2 hha&memhha reg i ster d ev i ce w i t h hi t pr i or i ty l ast d ev i ce *2
9-8 address processor ke5b256b1 fig. 9.6.1 priority decision timing in a cascaded system accessed in the device select method. refer to table 13.4 in chapter 13 for access availability in the broadcast method/ device select method of each register and the device ac- cessed in the broadcast method. table configuration table configuration must be common to all devices in a cas- caded system. it is recommended to write tc data in the broadcast method when the tc data is written to the memar register in the tc sub-mode. the memar reg- ister should be accessed in the device select method except for the table configuration. readout of search results the search results are stored in three registers, the hha register, the memhha register, and the hstat register in cpu search, and stored in five registers, which include the above three registers, the cmp register and the sh reg- isters in ip search. when the search results are read through the cpu port, the broadcast method is normally used. when these registers are read in the broadcast method, as for the hha and the memhha registers, the device with hit priority automatically outputs the data. as for the cmp register, the last device outputs the data because all de- vices store the same data. as for the hstat register, the last device outputs the data to indicate the hit/multi hit information of a whole cascade system. as for the sh reg- ister, the register can be read in the device select method because the sh register of each device stores its own search results in every ip sequence number. the hha register, the memhha register, and the hstat register can be accessed in the device select method to read each device's own information. some time is needed to propagate hit information and de- termine hit priority according to the number of cascaded devices. propagation delay in the cascaded system must be considered when the hha register, the memhha register or the hstat register is accessed after a search operation. in the next section, a discussion of detailed timing in a cas- caded system is shown. command execution when a command is executed in a cascaded system, the command should be executed by the broadcast method. in this case, the device to which the command execution ap- plies is automatically decided internally. it is not necessary to specify each device. it is possible to execute commands at a specified device, but the changes in the device to which commands are ex- hi_, pi_, fli_ wr, rd_, ce_ ho_, po_, flo_ valid t1 t2 t3 valid pulse 1 pulse 2 signal propagation
9-9 address processor ke5b256b1 table 9.7.1 relations between operation which changes priority and operation which needs priority determination pulse 1 operation which changes priority pulse 2 operation which needs pins priority determination to cons ider hit priority propagation wr search rd_ op output hi_, ho_, rd_ op output pi_, po_ ce_ register read/write ce_ register read/write hi_, ho_, hha register hha register (pi_, po_) automatic increment memhha register memhha r e g i s t e r memhha _ a t r e g i s t e r entry automatic increment hstat register * 1 command t command s rch command prg_hh command s rch2 command nxt_hh command gen_ hit command s tmp_ hh command nxt_hh command s tmp2 _hh command stmp_hh command * 1 in the operations through the cpu port, hha automatic increment only the hstat register operation must consider stmp2_hh command pi_, po_ instead of hi_, ho_. hha automatic increment for wr => wr, rd_=> wr and ce_=> wr, srst command the timing design is the same as single device (rst_pulse) and no special timing consideration is needed. empty priority propagation ce_ register read/write ce_ register read/write fli_, flo_ hea register hea register automatic increment memhea register memhea r e g i s t e r memhea _ a t r e g i s t e r entry automatic increment estat register command command gen_ fl command append command nxt_he command t append_nhe command s tmp_ he command nxt_he command hea automatic increment stmp_he command s tmp2 _he command s tmp2 _he command hea automatic increment append_nhe command wr and rd_ puls e have no relation to srst command the empty priority changing and determination. (rst_pulse) devid priority propag ation * 2 no special timing consideration * 2 pi_, po_ propagates the devid priority when the mode is the devid sub mode after the str_devid comman d execution. pi_, po_ propagates multi-hit information when the devid mode ends after the devid_end command execution. 1 s waiting time must be taken after the devid_end command to await the status of pi_, po_ being stable.
9-10 address processor ke5b256b1 ecuted will propagate to other devices. it must therefore be noted that the system-level information such as status and flags may change. chapter 12 shows the detailed command executable conditions. 9.7 ac characteristics in a cascaded system this device can automatically perform its internal control function by using respective priority signals. after priority changes by some action, the next operation which needs priority determination must wait a certain time according to the number of cascaded devices. as shown in fig. 9.7.1, the total time required between pulse 1 and pulse 2 for priority determination amounts to (t1+ t2+ t3) . here, t1, t2, and t3 are defined as follows: t1: delay time from pulse 1 to the priority signal in the top device t2: delay time of priority signal from the top device to the last device t3: setup time of the priority signal to pulse 2 of the last device table 9.7.1 shows the relationship between pulse 1 (the op- eration which causes a priority change) and pulse 2 (the operation which requires a priority decision). the operation which causes a hit priority change is either search operation (ip search, cpu search), or the incrementation of the hha register. the increment action of the hha includes the incrementation caused by the au- tomatic increment function described in section 8.6. the hit priority also changes when the search result is read through the output port. the operation which requires a hit priority decision is the operation which refers to the hha register. such operation includes the register access/command execution through the cpu port, and reading search results through the out- put port. as for reading the hstat register through the cpu port and reading search results through the output port (op se- quence), they need not only the determination of hit priority but also the determination of multi-hit information. the hit priority is propagated with the hi_ and the ho_ pins and the multi-hit information is propagated with the pi_ and the po_ pins. the operation which causes an empty priority change is the operation that the hea register changes, which is the gen_fl command and incrementation of the hea regis- ter. the increment action of the hea includes the incrementation caused by the automatic increment function described in section 8.6. the operation which requires an empty priority decision is the operation which refers to the hea register. such op- eration includes the register access/command execution through the cpu port. there is no need to wait for the empty priority decision for the access through the input port and the output port. timing design considering priority propagation , as de- scribed above, is necessary. some examples are shown below to explain the timing de- sign of cascaded systems. example 1: wr ? ? ? ? ? wr the time difference rule between a wr pulse and the next wr pulse in a cascaded system is the same as the rule in single device (min. cycle 80 ns), because the ip search is executed simultaneously at all devices. the ho_ and po_ pins of the last device must be monitored to know the search results of the whole cascaded system caused by a wr pulse. the time from the wr pulse to a valid ho_, po_ output will be longer in proportion to the number of cascaded devices increasing. in the cycle to monitor the ho_ and po_ pins, there needs to be enough time to the next wr pulse.
9-11 address processor ke5b256b1 fig. 9.7.2 example of timing design in a cascaded system ( wr ? rd_ ) hi_ pi_ rd_ ho_ po_ 100 ns 70 ns wr *1 *5 hi_ pi_ rd_ ho_ po_ 20 ns wr *3 hi_ pi_ rd_ ho_ po_ 20 ns wr *3 hi_ pi_ rd_ wr 10 ns ho_ po_ wr rd_ m cascaded devices *2 *2 valid valid signal propagation wr po_ (top) pi_ (last) t1 t2 t3 rd_ t ? t ? *4
9-12 address processor ke5b256b1 example 2: wr ? ? ? ? ? rd_ the example of the timing design, when the search results are output through the output port after ip search, is shown in fig. 9.7.2. to simplify the example, the line delay time between devices is supposed to be constant d t. the ho_ and po_ pins will be changed after the ip search caused by a wr pulse. the ho_, po_ output of each de- vice will be valid 70 ns, 100 ns after. the time from the ho_, po_ valid output of one device to the ho_, po_ valid output of the next device is (20 ns + d t), considering 20 ns internal delay time from the hi_, pi_ input to ho_, po_ output. the total delay time until the hi_, pi_ input of the last device is determined is (70 ns + d t * (m-1) + 20 ns * (m-2)), (100 ns + d t * (m-1) + 20 ns * (m-2)) respec- tively. the setup time of the hi_, pi_ input to the rd_ pulse is 10 ns. finally, (100 ns + d t * (m-1) + 20 ns * (m-2) + 10 ns) must be taken from the wr pulse to the rd_ pulse because the total delay time of the po_ output is longer than that of the ho_. the ho_, po_ output of the last device are valid at (70 ns + d t * (m-1) + 20 ns * (m-2)), (100 ns + d t * (m-1) + 20 ns * (m-1)) after the wr pulse. example 3: rd_ ? ? ? ? ? rd_ the ho_ and po_ pins will be changed also after the rd_ pulse in the op sequence. (100 ns + d t * (m-1) + 20 ns * (m-2) + 10 ns) must be taken from the rd_ pulse to the rd_ pulse because the total delay time of the po_ output is longer than that of the ho_ , in the same way as example 2. example 4: wr ? ? ? ? ? ce_ the hit priority must be determined to read the hha regis- ter. in fig. 9.7.3 (a), the hi_ setup time to ce_ (10 ns) is needed and the delay time of the hi_ and ho_ must be considered for the timing design. the time from the wr pulse to the ce_ pulse to read the hha register is (70 ns + d t * (m-1) + 20 ns * (m-2) + 10 ns) . the pi_ setup time to ce_ (10 ns) is also needed to read the hstat register, not only the hi_ setup time. the de- lay time of the pi_ and po_ must be considered for the timing design. the time from the wr pulse to the ce_ pulse to read the hstat register is (100 ns + d t * (m-1) + 20 ns * (m-2) + 10 ns) . there are various actions caused by a ce_ pulse, and all of them don't need to determine the hit priority. when the reg- ister which is not related to the ip search and the search results output is set, the ce_ pulse can be applied before the timing described above. example 5: ce_ ? ? ? ? ? ce_ the timing design between one ce_ pulse to the next ce_ pulse, considering the propagation of the empty priority, will be explained using example of fig. 9.7.4. the flo_ output will be changed by the gen_fl command. it takes 70 ns to determine the flo_ output in each device. the time from the flo_ valid output of one device to the flo_ valid output of the next device is (20 ns + d t), considering a 20 ns internal delay time from the fli_ input to the flo_ output. the total delay times until the fli_ input of the last device is determined is (70 ns + d t *(m-1) + 20 ns * (m-1)). the setup time of the fli_ input to ce_ pulse to read the hea register is 10 ns. (70 ns + d t * (m-1) + 20 ns * (m-2) + 10 ns) must be taken from the gen_fl com- mand to the hea register read. there are various actions caused by a ce_ pulse and all of them don't need to determine the empty priority. the timing design that the priority determination considers can be eas- ily done by inserting dummy cycles like the nop command,
9-13 address processor ke5b256b1 if the cycle time of the ce_ is short (min. 80 ns). detailed ac characteristics are shown in chapter 14. 9.8 single device operation a device reset automatically sets the device id to "00000" and the ld to meaning the last device. therefore, it is not necessary to set the device id by using the devid sub- mode in the case of single device operation. the hi_ and pi_ must be pulled up and the fli_ must be pulled down with the single device. the device acts as one with hit/empty priority, if there is any hit/empty entry in the device. on the other hand, it acts as the last device if there is no hit/empty entry in the de- vice. there fore, the behavior is the same in the broadcast method as in the device select method, but some commands must be executed in the device select method according to the condition of table 12.2, and some registers must be accessed in the device select method according to the con- dition of table 13.4, even in this case.
9-14 address processor ke5b256b1 fig. 9.7.3 example of timing design in a cascaded system ( wr ? ce_ ) hi_ pi_ ce_ ho_ po_ 100 ns 70 ns wr *1 *5 hi_ pi_ ce_ ho_ po_ 20 ns wr *3 hi_ pi_ ce_ ho_ po_ 20 ns wr *3 hi_ pi_ ce_ wr 10 ns ho_ po_ wr ce_ m cascaded devices *2 *2 valid valid signal propagation wr po_ (top) pi_ (last) t1 t2 t3 ce_ hstat valid valid signal propagation wr ho_ (top) hi_ (last) t1 t2 t3 ce_ hha t ? t ? *4
9-15 address processor ke5b256b1 fig. 9.7.4 example of timing design in a cascaded system ( ce_ ? ce_ ) fli_ flo_ 70 ns ce_ *1 fli_ flo_ 20 ns ce_ *3 flo_ 20 ns ce_ *3 fli_ ce_ flo_ ce_ m cascaded devices *2 *2 10 ns *4 fli_ flo_ valid ce_ flo_ (top) fli_ (last) t1 t2 t3 valid signal propagation hea read gen_fl command t ? t ?
10-1 address processor ke5b256b1 10. initialization there are two types of initialization for this device: device reset for device initialization, and sequence pointer reset for sequence pointer initialization. device reset must be done after the power is on. sequence pointer reset initializes the ip sequence pointer, the op se- quence pointer and the op sub-sequence pointer. note that the device reset does not contain the function of the se- quence pointer reset. device reset device reset is performed by a low pulse to the rst_ pin or by an srst command . device reset executes the fol- lowing initialization: ? initializes device id *1 ? erases tc data *2 ? initializes registers *3 ? sets empty bits of all entries (all entries are empty) ? resets hit fags and access bits of all entries ? ho_ = "high" (no hit) ? po_ = "unknown" *4 ? flo_ = "unknown" *5 ? sh0_, sh1_= "high impedance" (no hit) ? selects cpu mode (sp/tp_ pull down) ? ipbusy/opact_ = "low", opbusy_/ipact_ = "low" (sp/tp_ pull down) ipbusy/opact_ = "high", opbusy_/ipact_= "high" (sp/tp_ pull up) ? initializes toggle control of endian *6 ? initializes segment counters for memhha, mhmhea register access (segment number becomes "0") *1 device ids must be registered when devices are cas- caded. *2 table configuration must be executed after device re- set. *3 the initial values of registers are shown in chapter 13. *4 the state of po_ is unknown until a search operation is executed. *5 the state of flo_ is unknown until a gen_fl com- mand is executed. *6 endian is on and the toggle pointer points to the h side. sequence pointer reset sequence pointer reset is performed by a low pulse to the sqrst_ pin or by an ssqrst command. sequence pointer reset executes the following initialization: ? initializes ip sequence pointer *1 ? initializes op sequence pointer and op sub-sequence pointer *2 ? sh0_, sh1_= "high impedance" (no hit) ? sh register = "00000000" ? interrupts ip sequence/op sequence *3 *1 the configuration of the ip sequence is not changed. at this time, the active channel and the start sequence number i are read. (see chapter 6) *2 the configuration of the op sequence is not changed. at this time, the active channel and the start sequence number/start sub-sequence number i are read. (see chapter 7) *3 when the ip sequence/op sequence is in progress
11-1 address processor ke5b256b1 11. examples some examples will be shown in this chapter. example: 1 typical operation flow fig 11.1 shows the typical operation flow, from the initial- ization after the power is on, to the table configuration, the operations through the input/output port. in this ex- ample, the entry is 64 bits in width (2 segments), which consists of two parts, one is a 48-bit width search data area and the other is a 16-bit width attribute data area which is output after hit. the sp/tp_ is pulled down and internal automatic control is used. simple ip/op sequences are used in this example. a 48-bit search is executed in 2 steps in the ip sequence, consisting of a 32-bit search in the first step and a 16-bit search in the second step. the op sequence is one step to read the 16-bit attribute data of the hit entry. it is suggested that if multi- hit doesn't happen in this example, the memhha output in the op sequence is set to "one". data is written to the table by using the automatic incre- ment function of the memhea register. it is also possible to write the data by using the memar register with a specifying cam address. the swiop command is executed before operations through the input/output port, and a sequence pointer reset is executed. if there is a hit after the ip sequence execution, then the attribute data for the hit entry is output in the op sequence. another sequence pointer reset is needed to re- start the ip sequence. if it is needed to rewrite the table data, write operations are executed suitably through the cpu port. (the cpu interrupt command is executed, if necessary.) if there is no hit after the ip sequence execu- tion, the operations through the cpu port such like the ap- pend command are executed when necessary. if the sp/tp_ pin is pulled up to select the external arbitra- tion, there is no need to use the swiop command or the cpu interrupt command. but the external arbitration is needed to avoid the conflict of the operations from the ports. example: 2 register search key data of mishit (ap- pend) fig. 11.2 shows the example of the append operation rou- tine. the append operation is that the search key data is registered to the table when the search result is mishit. it is used for the source address learning of the bridge/hub. the entry configuration of this example is the same of fig. 11.1. an additional entry is registered by the operations thor- ough the cpu port when the search result is mishit. the search key data is copied to the entry pointed by the hea register at the end of the search, as described in chapter 8. the 16-bit width attribute data is written to the table by writing to the memhea register with endian off. only one cycle is consumed for this operation. after that, the append command makes this entry valid. if the segment numbers 0/1 are reversed, the entry is valid at writing to the memhea register and the append command can be omitted. because the attribute data is written to the head segment (segment number 0). then the gen_fl command should be executed. if the append_nhe command is used to substitute the ap- pend command, the gen_fl command is not needed. if the sp/tp_ pin is pulled up to select the external arbitra- tion, these operations do not need the mode transition.
11-2 address processor ke5b256b1 fig. 11.1 example of typical operation flow 48-bit width search data 16-bit width attribute data segment number 0 segment number 1 64 bits entry configuration power on sp/tp_pull down (internal arbitration) device reset(rst_=low) devid must be registered in the devid sub-mode, when multiple devices are cascaded. initialize through the cpu port cntll register write cntlh register write entry size definition (ww<2:0>=001) endian setting (from l side), input port width (32 bits) etc. str_tc command table configuration ar register write memar re g ister write even cam address ... tc data = 1000 odd cam address ... tc data = 0001 end_tc command gen_fl command ip/op sequence configuration cntll re g ister write a ch cut re g ister write ss register write cs register write mask re g ister write aoc register write aoc0_ aoc7 aosc register write aosc0_ aosc7 go to next page cut0l_ cut1h ss0l_ ss1h cs0_ cs7 mask0l_ mask7h ip/op active channel = b ... a ch can be written (ia<2:0>=oa<2:0>=001) ? 32 bits width x 2 blocks search ? ip sequence number 0 segment number 0, search head 0 byte shift, no mask access bit set off ? ip sequence number 1 se g ment number 1, and search 2 byte shift, lower 16 bits mask access bit set on sequence end ? op sequence number 0 memhha output, one, not mixed sequence end ? op sub sequence number 0 segment number 1 output, not mixed sub-sequence end
11-3 address processor ke5b256b1 fig. 11.1 example of typical operation flow (cont'd) cntll register write b ch cut register write ss register write cs register write mask register write aoc register write aoc0_ aoc7 aosc register write aosc0_ aosc7 cut0l_ cut1h ss0l_ ss1h cs0_ cs7 mask0l_ mask7h table making cpuhsl register write ip/op active channel = a ... bch can be written (ia<2:0>=oa<2:0>=000) memhea automatic increment = segment & entry automatic increment (em<1:0>=11) memhea re g ister write(se g ment number 0, l) memhea register write(segment number 0, h) memhea register write(segment number 1, l) memhea re g ister write(se g ment number 1, h) repeat until all desired entries are written gen_fl command swiop command to this point in the cpu mode operation through the input/output port sequence pointer reset first search : 32-bit search (se g ment number 0) second search : 16-bit search (segment number 1) se g ment number 1 data output ip sequence hit op sequence ip ... ach, start sequence number0 op ... ach, start sequence number 0, start sub-sequence number 0 cpu interrupt procedure after missed hit (append, etc. , if necessary) miss hit
11-4 address processor ke5b256b1 fig. 11.2 example of registering search key data of a missed hit (append) cntlh register write (endian off) ip sequence first search : 32-bit search segment number 0 (32 bits) second search : 16-bit search segment number0 (lower 16 bits masked) swcpup command *1 memhea re g ister write *2 append command *3 gen_fl command *4 swiop command *1, 4 (cpu mode)*1 *1 mode transition is not needed when sp/tp_is pulled up. *2 when endian is fixed to l. there are some cases that the stmp_he and the stmp2_he commands are more effective according to the position of the attribute data. *3 the append command is not needed when the attribute data is located in se g ment number 0. *4 the gen_fl command is not needed when the append_nhe command is used instead of the append command. and the swiop command is not needed when the append_nhe command with automatic swiop enable is used. segment number 0 segment number 1 48-bit width search data 16-bit width attribute data x 1 1 1 1 0 xxx xx data copy data copy attribute data write entry configuration empty bit hea
11-5 address processor ke5b256b1 example 3: table aging with the access bit table aging is the table management system based on the information whether the entry has been manipulated re- cently or the entry has not been manipulated for long time. there are various ways to achieve table aging. in fig. 11.3, an example of simple aging with the access bit is shown. the access bit stores the history of the hit. if an entry has no hit for a certain time, the access bit of the entry is not set. the entries which have no hit for a certain time can be purged all at once by the prg_nac command. one of the simplest aging can be done by using the bi-level informa- tion whether there is a hit or not for a certain time. there is a case that the entry which doesn't have a hit for a certain time is made to stay (not to purge). this entry is called permanent entry or static entry. permanent bit , 1- bit flag, is prepared in the data area of an entry. this flag is set to "1" for the permanent entries, "0" for other entries. consider the situation that the hit history of searches in a certain period is stored to the access bit as in fig. 11.3 (a). when the entry which doesn't have a hit in the period (the access bit is "0" ) is purged, the permanent entries can be protected from purging by the following procedure: first, the srch command is executed to make hits to the entries where the permanent bit is "0". in this example, the srch command is used. the srch2 command, using the cpuinp2 and the cpumask2 registers, also can be used instead of the srch command. after the srch command execution, the entries achieve the status shown in fig. 11.3 (b). there are three entries, entry numbers 2, 4, and 6, where the access bit is "0" and the hit flag is "1". these three entries will be purged if the prg_nacwh command is executed in this situation. the permanent en- tries will not be purged because the hit flag of the perma- nent entry is "0". the access bit of the entry number 0 and 1 is "0," but they are not purged and stayed in the table. besides, the access bits of all entries other than the per- manent entries are cleared when the prg_nacwh com- mand is executed. the gen_fl command and the gen_hit command must be executed after the purge. the access bit is not set for the entry which is newly reg- istered in the period by the append command or other commands. it is difficult to set the access bit of the entry which is registered just before the purge time by a hit oc- currence. the entry is very like to be purged. to avoid this situation, it is recommended to write "1" to the access bit by using the at registers when the entry is newly regis- tered.
11-6 address processor ke5b256b1 fig. 11.3 example of table aging with access bit 1 1 0 0 0 1 0 0 0 1 2 3 4 5 6 7 entry number permanent entry (static entry) permanent bit entry data hit flag 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 access bit empty bit (a) the status that the access bits store search results after some ip sequence steps are executed 0 0 cpuinp cpumask search permanent bit = 0 (other bits are masked) srch command execution *access bit is not set in this search 1 1 0 0 0 1 0 0 0 1 2 3 4 5 6 7 entry number permanent bit hit fla g 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 access bit empty bit 0 0 1 1 1 0 1 1 entry of access bit = 0 hit flag = 1. (b) status just after srch command execution go to next page
11-7 address processor ke5b256b1 fig. 11.3 example of table aging with access bit (cont'd) prg_nacwh command execution the entry of access bit = 0 and hit fla g = 1 is pur g ed, and the access bit of the entry of hit fla g = 1is cleared simultaneously. (b) status just after prg_nacwh command execution gen_fl , gen_hitcommand execution 1 1 0 0 0 1 0 0 0 1 2 3 4 5 6 7 entry number permanent bit hit flag 0 0 0 0 0 1 0 0 0 0 1 0 1 0 1 0 access bit empty bit 0 0 1 1 1 0 1 1 1 1 0 0 0 1 0 0 0 1 2 3 4 5 6 7 entry number permanent bit hit flag 0 0 0 0 0 1 0 0 0 0 1 0 1 0 1 0 access bit empty bit 0 0 0 1 0 0 0 1 the empty bit of each is reco g nized a g ain and the hit fla g s of entry numbers 2 and 4 are reset. (c) status after gen_hit command
11-8 address processor ke5b256b1 example 4 : table aging with time stamp the table aging with the access bit, described in example 3, uses the information whether there is a hit or not in the period to determine the entries to purge. it cannot distin- guish a recently hit entry from an entry which was hit some time ago. the table aging with time stamp can distinguish the hit entries in detail by using the information of hit time. time stamping is done to record the time when the entry is hit or registered for each entry. the desired width of the time stamp data area needs to be made in the entry data area to execute the table management with the time stamp as shown in fig. 11.4. if the width of the time stamp area is wider, more detailed aging can be executed. the hit time is written to this area for the hit entry and the registered time is written for the appended entry by the stamp commands. fig. 11.3 (a). shows the stamp procedure for the hit entry and the stamp procedure for the appended entry. the stmp2_hh command is used for the hit entry and the stmp2_he command is used for the appended entry, in order to stamp. the segment number to be stamped, seg- ment number 1 in this example, is written to the cpusrs2 register and the mask data to mask the area, ex- cept the time stamp data area is written to the cpumask2 register before stamping. the time data to stamp is written to the cpuinp2 register and the register is rewritten peri- odically through the cpu port. the time data stored in the cpuinp2 register is written to the entry when the stamp commands (stmp2_hh, stmp2_he) are executed. fig. 11.3 (b). shows the procedure to purge old data and renew the table. in this example, "t1" is the oldest time value and the entry which has time stamp data "t1" is purged. the entry stamped "t1" is picked up by the srch command. the access bits of all "t1" stamped en- tries are set by setting the access bit in the srch com- mand. when using the table management with stamp, the access bit is not set in normal search operation and the access bit is only set in the cpu search to pick up the entry to be purged. after that, the prg_ac command is executed to purge all "t1" stamped entries. the entries of one time stamp (for example "t0") and the entries of another time stamp (for example "t1") can be purged at once easily by changing the data of the cpumask register at the srch command ex- ecution. the permanent entry, described in example 3, can also be supported easily by considering the permanent bit at the srch command execution. in this example, the stmp2_hh command and the stmp2_he command are used to stamp, but the stmp_hh command and the stmp_he command can also be used. the srch2 command can be used for the cpu search in the purge procedure. when using these com- mands, care must be taken to use the correct register set. the operation must be sure that the way to specify the seg- ment number to stamp of the stmp_hh command and the stmp_he command is different from the way of the stmp2_hh command and the stmp2_he command. a detailed command description is shown in chapter 8 and chapter 12. in the stamp procedure shown in fig. 11.4 (a), and the purge procedure shown in fig. 11.4 (b), the mode transition commands like the swcpup command and the swiop command are only needed when the sp/tp_ pin is pulled down and the internal arbitration is used.
11-9 address processor ke5b256b1 fig. 11.4 example of table aging with time stamp 48-bit width search data segment number 0 segment number 1 attribute data time stamp data t mask cpuinp2 register cpumask2 register t hit entry of appended entry cpu rewrites data periodically t0->t1->... hit time or appended time is recorded * confi g ure not to set the access bit in normal search. if necessary if necessary stamp to hit entry search hit search result output (swcpup command) stmp2_hh command (swiop command) return to ip/op sequence (sequence pointer reset, etc.) stamp to appended entry search miss hit (swcpup command) attribute data registration by memhea register write stmp2_he command append command, gen_fl command *1 (swiop command) if necessary if necessary *1 the append command is not needed when segment number 0 is in the stamp data area. in addition, the gen_fl command and the swiop command are not needed when the stmp2_he command with automatic increment enable and automatic swiop enable is executed during that time. (a) stamp procedure
11-10 address processor ke5b256b1 fig. 11.4 example of table aging with time stamp (cont'd) table status at a certain time t2 t0 t1 t2 t3 t0 t1 after the entry which has time stamp " t1 " t2 t0 t2 t3 t0 empty empty purge routine in a certain time (t1 is the oldest time value) (swcpup command) cpuinp register write " t1 " srch command (access bit set) prg_ac command gen_fl command (swiop command) return to ip/op sequence (sequence pointer reset, etc.) if necessary if necessary cpumask = " mask other than t area " cpusrs = " access bit set on, search head, segment number 1" in advance (b) pur g e procedure
12-1 address processor ke5b256b1 table 12.1 command table 12. command descriptions 12.1 command functions all commands are executed by writing data into the com register. table 12.1 shows the command names, operation codes, functions and descriptions. the condition for command execution is different for each command. when the sp/tp_ pin is pulled down and the internal arbitration is used, some commands can be ex- ecuted only in the cpu mode. basically, commands are command command name function des cription group (op-code) srst software executes device reset. the function of this command reset (00h) reset is the same as a low pulse input to the rst_pin. ssqrst sequence pointer initializes the ip sequence pointer, but the contents for (01h) reset the ip configuration are unchanged. the function of this command is the same as a low pulse input to the sqrst_pin. s tr_ devid devid s ub-mode s wi tc h e s th e de bi c e to devid s ub-mode i n or de r to s e t (20h) start up the device id. confi g ur ati on end_ devid devid s ub-mode ends the devid s u b-mode . (21h) end nxt_pr shift devid shifts the devid priority to the next device in the (2 2 h) p r i or i ty devid s ub-mode . str_tc tc sub-mode switches the device to the tc sub-mode in order to (23h) start execute table configuration. end_ tc tc s u b-mode ends the tc s ub-mode . (24h) end swcpup switch to the cpu mode requests an interruption from the cpu port. if the device (40h) is in the iop mode, the swcpup command switches the device to the cpu mode immediately. if the device is in mode change the ip mode or the op mode, the mode is switched after *1 the end of the ip sequence or op sequence. swcpup_im quick switch to the requests an interruption from the cpu port. if the device (41h) cpu mode is in the iop mode, the swcpup_im command switches the device to the cpu mode immediately. if the device is in the ip mode or the op mode, the mode is switched at the end of the next cycle without waiting for the sequence to end. see chapter 14 for detailed timing. swcpup_sqe switch to the cpu requests an interruption from the cpu port. if the device (43h) mode at sequence end is in the ip, op or iop modes, the swcpup_sqe command switches the device to the cpu mode after the end of the ip sequence or the op sequence. the function of this command is different from the swcpup command only when executed in the iop mode. if the device is in the iop mode, the interruption request is reserved and the mode is switched after the end of the ip sequence or the op sequence. swiop switch to the iop mode switches the device to the iop mode. (42h)
12-2 address processor ke5b256b1 table 12.1 command table (cont'd) executed with the broadcast method in a cascaded system, but some commands must be executed with the device se- lect method. the conditions for command execution are shown in table 12.2. command command name functi on des cri pti on group (op-code) cam table srst cpu search issues the search operation command from the cpu control (60h) port. it is necessary to set the key data, the segment number and the mask pattern for each search operation. this command uses cpuinp, cpumask, cpusrs registers for these settings. srch2 cpu search issues the search operation command from the cpu (76h) port. it is necessary to set the key data, the segment number and the mask pattern for each search operation. this command uses cpuinp, cpumask, cpusrs registers for these settings. prg_al *2, 3 purge all entries in purges all entries in the cam table. all empty (61h) the cam table bits are set and all access bits are cleared. prg_nac *2, 3 purge all purges all entries whose access bits are not set (no hit (62h) "no access bit set" career). the empty bits of purged entries are set and entries the access bits of all entries are cleared. prg_ac *2, 3 purge all purges all entries whose access bits are set (hit career). (63h) "access bit set" the empty bits of purged entries are set and the access entries bits of all entries are cleared. prg_hh *2, 3 purge entry sets the empty bit of the entry indicated by the hha (64h) indicated by the register to purge. the access bit of the entry is cleared. hha register prg_ar *2, 3 purge entry sets the empty bit of the entry indicated by the ar (65h) indicated by the register to purge. the entry address (cam address of the ar register head segment) of the entry to be purged should be written to the ar register. the access bit of the entry is cleared. rst_ac clear all access bits clears all access bits. (66h) prg_nacwh purge all purges all entries whose access bits are not set (no hit (74h) *2, 3 "no access bit set" career) and hit flags are set in last search. the empty and " hit flag s et " bits of purg ed entries are s et and the acces s bits of all entries entries are cleared. prg_acwh purge all purges all entries whose access bits are set (hit career) (7 3h) * 2, 3 "acces s bit s et" and hit flags are s et in las t s earch. the empty bits of and " hit flag s et " purged entries are s et and the acces s bits of all entries entries are cleared. rst_acwh clear all access bits of clears all access bits of the entries whose hit flags are (75h) " hit flag set " entries set in last search.
12-3 address processor ke5b256b1 table 12.1 command table (cont'd) command command name functi on des cri pti on group (op-code) cam table nxt_hh renew the makes the hha register store the entry address with the control (67h) hha register next hit priority. the content of the hstat register and the s tatus of the ho_ andpo_ pins are als o changed. this command is used for reading out the information of all hit entries. gen_hit return the returns hha register to the state immediately after the (68h) hha register search operation. the content of hatat register and the s tatus of ho_ andpo_ pins are als o changed. nxt_he return the makes hea register store entry address with next hit (69h) hha register priority. the content of estat register and the status of flo_pins are als o chang ed. gen_fl confirm the confirms the empty s tate the of cam table. makes the (68h) hea register hea register store the entry address with the highest empty priority. the content of the estat register and the s tatus of the flo_pin are als o chang ed. append *2 , 4 add s earch key adds us ed key data in the empty entry of the cam (6ch) data to the table table indicated by the hea register append_ nhe add s earch key data adds us ed key data in the empty entry of the cam table (6eh) *2, 4 to the table and renew designated by the hea register and renews the hea the hea register register. the content of the estat register and status of the flo_ pin are als o changed. this command contains both functions of the append command and the nxt_he command. restore *2 restore entry resets the empty bit of the entry designated by the ar (6dh) register to " valid. " the desired entry address (cam addres s of the head s eg ment) s hould be s et in the ar register. this command is used to make a purged entry valid ag ain. stmp_ar *5 stamp entry moves the 32-bit data in the cpuinp register into the (70h) indicated by the segment of the entry indicated by the ar register. ar register masked bits defined by thecpumask register are not changed. stmp2_ar *5 stamp entry moves the 32-bit data in the cpuinp2 register into the (77h) indicated by the segment of the entry indicated by the ar register. ar register masked bits defined by the cpumask2 register are not changed.
12-4 address processor ke5b256b1 table 12.1 command table (cont'd) *1 when the sp/tp_ pin is pulled up and the external arbi- tration is used, these commands are not needed. *2 the status of the hea register and the estat register and the state of the flo_ pin are not correct after the ex- ecution of this command. it is necessary to update their status by using the gen_fl command. *3 the status of the hha register and the hstat register and the state of the ho_ pin are not correct after the execu- tion of this command. it is necessary to update their status by using the gen_hit command. *4 the device moves into the iop mode after this com- mand when the apm bit in the cpuhs register is set to "1" and the command is executed (in the case of internal arbi- tration). *5 the device moves into the iop mode after this com- mand when the stm bit in the cpuhs register is set to "1" and the command is executed (in the case of internal arbi- tration). *6 the hha register is renewed when the shi bit in the cpuhs register is set to "1" and the command is executed. *7 the hea register is renewed when the sei bit in the command command name functi on des cri pti on group (op-code) cam table stmp_hh *5, 6 stamp entry moves the 32-bit data in the cpuinp register into the control (71h) indicated by the entry indicated by the hha register. the segment to be hha register stamped is indicated by the cpuhs register. the method of automatic increment access to the memhha register should be set as " no increment. " masked bits defined by the cpumask register are not changed. stmp2_hh *5, 6 stamp entry moves the 32-bit data in the cpuinp2 register into the (78h) indicated by the entry indicated by the hha register. the segment to be hha register stamped is indicated by the cpusrs2 register. masked bits defined by the cpumask2 register are not changed. stmp_he *5, 7 stamp entry moves the 32-bit data in the cpuinp register into the (72h) indicated by the entry indicated by the hea register. the segment to be hea register stamped is indicated by the cpuhs register. the method of automatic increment access to the memhea register should be set as " no increment." masked bits defined by the cpumask register are not changed. this command i s us e d to s tamp the e ntr y ne wl y-adde d by th e append command. stmp2_he *5, 7 stamp entry moves the 32-bit data in the cpuinp register into the (79h) indicated by the entry indicated by the hea register. the segment to be hea register stamped is indicated by the cpusrs2 register. masked bits defined by the cpumask2 register are not changed. this command is used to stamp the entry n e wl y-adde d by the append c omman d. other nop no operation executes no operation. this command is us ed to adjus t (80h) the timing to the host processor.
12-5 address processor ke5b256b1 table 12.2 command executable conditions 12. 2 conditions for executing commands command srst ssqrst str_devid end_devid nxt_pr str_tc end_tc swcpup swcpup_im swcpup_sqe swiop srch srch2 prg_al prg_nac prg_ac prg_hh prg_ar rst_ac prg_nacwh prg_acwh rst_acwh nxt_hh gen_hit nxt_he gen_fl append append_nhe restore stmp_ar stmp2_ar stmp_hh stmp2_hh stmp_he stmp2_he nop device selection broadcast *1 device select mode when internal arbitration (sp/tp_=low) is used. executable mode after execution *5 *5 *7 *7 *7 *5 *5 *7 *7 *2 *2 *2 *2 *2 *2 *2 *2 *2 *2 *2 *6 *6 *8 *8 *8 *6 *6 *8 *8 cpu(devid) devid devid cpu tc cpu cpu cpu cpu cpu cpu cpu cpu cpu cpu cpu cpu cpu cpu cpu cpu cpu cpu cpu cpu cpu cpu cpu cpu cpu cpu iop(cpu) *3 devid cpu unchanged tc cpu cpu *4 cpu *4 cpu *4 iop unchan g ed unchan g ed unchanged unchanged unchan g ed unchanged unchanged unchanged unchan g ed unchan g ed unchan g ed unchanged unchanged unchanged unchanged unchanged (iop)*9, 10 unchanged (iop)*9 unchanged unchanged (iop)*9 unchan g ed (iop)*9 unchan g ed (iop)*9 unchanged (iop)*9 unchan g ed (iop)*9, 11 unchan g ed (iop)*9, 11 unchan g ed : any mode : executable : executable (device not selectable) : not executable
12-6 address processor ke5b256b1 cpuhs register is set to "1" and the command is executed. *1 all commands except prg_hh, prg_ar, nxt_hh, nxt_he, append, append_nhe, restore, stmp_ar, stmp2_ar, stmp_hh, stmp2_hh, stmp_he, stmp2_he are executed for all devices. *2 the command is executed for all devices (a device can- not be selected). *3 the device is switched to the iop mode when the com- mand is executed in the ip mode or op mode. but, the mode is not changed when the command is executed in the cpu mode. *4 see table 12.1 and chapter 14 "ac characteristics" for the timing switch to the cpu mode. *5 only the device with hit priority accepts the command. (the command is not executed when there is no device with hit priority.) *6 the command is not executed when the selected device doesn't have hit entry. *7 only the device with empty priority accepts the com- mand. (the command is not executed when there is no de- vice with empty priority.) *8 the command is not executed when the selected device doesn't have an empty entry. *9 if the automatic swiop is enabled, the device is switched to the iop mode after the command is executed. *10 when the automatic swiop is enabled and appending an entry, the append_nhe command is recommended. *11 when the automatic swiop is enabled and either the stmp_he command, or the stmp2_he command is ex- ecuted, the automatic increment of the hea register should also be enabled by setting the sei bit in the hea register to "1."
13-1 address processor ke5b256b1 13. register descriptions 13.1 overview registers of the device are classified into six functional groups (command register group, control status regis- ter group, memory r/w register group, configuration register group, cpu search register group, table status register group). an overview of each register group is presented below. (1) command register group this group has only one register, the com register, which is used to execute commands by writing the op-code (see chapter 12). (2) control register group this group has three registers, the cntl, the devid, and the devstat registers. the cntl register speci- fies the condition of the operation of the ap, such as the endian and the input port bus width. the devid reg- ister is used to store the device id in a cascaded system. the devstat register is used to output the device status. (3) memory r/w register group this group has nine registers: devsel, ar, memar, memhha, memhea, cpuhs, memar_at, memhha_at, and memhea_at registers. the devsel register is used to select the device in a cascaded system. the ar register is used to specify the absolute address used for the read/write operation of the memar register. the memar register is used to read/write the contents of the cam table indicated by the ar register. the content that is stored at an entry address assigned by the hha and cpuhs register is read/ written via the memhha register. the content stored at an entry address assigned by the hea and cpuhs regis- ter is also read/written via the memhea register. the cpuhs register stores the automatic increment setting of the memhha and memhea registers, and the segment number for the next access. the access bit and empty bit indicated by the specified cam address can be read/writ- ten via the memar_at, memhha_at, and memhea_at registers. (4) configuration register group this group has eight registers: cut, ss, mask, cs, aoc, aosc, shasgn, hhaasgn registers. the cut, ss, mask, and cs registers are used for the ip configura- tion, and the aoc and aosc registers are used for the op configuration. the shasgn register is used to specify the sequence number of the ip sequence, the result of which is output on the sh0_ or sh1_ pins. (5) cpu search register group this group has six registers: cpuinp, cpumask, cpusrs, cpuinp2, cpumask2, and cpusrs2 regis- ters. in the search operation from the cpu port, it is necessary to write the data for each search operation into these registers. the cpuinp and cpuinp2 registers store the search key data. the cpumask and cpumask2 registers store the mask data. the cpusrs and cpusrs2 registers store the segment number for executing the search. furthermore, these reg- isters are also used to execute the stamp command. (6) table status register group this group has six registers, the hstat, the estat, the hha, the hea, the sh, and the cmp registers. the hstat and the estat registers store the status of hit/ empty of each device. the hha and the hea registers store the highest hit address and highest empty address ,respectively. the sh register stores each search result of
13-2 address processor ke5b256b1 every ip search sequence number. the cmp register stores the key data used in the ip sequence. the sh register stores the search results of each step of the ip sequence.
13-3 address processor ke5b256b1 table 13.2.1 register address 13.2 register addresses table 13.2.1 shows the register addresses. registers over 16-bit in width are divided by 16 bits. group register name address group register name address (1) command com 00h (4) configuration aoc0 60h (2) control cntll 02h aoc1 62h status cntlh 03h aoc2 64h devid 04h aoc3 66h devstat 06h aoc4 68h (3) memory r/w devsel 08h aoc5 6ah ar 0ah aoc6 6ch memar 0 ch aoc7 6 eh memhha 0 eh aos c0 7 0h memhea 1 0h aos c1 7 2h cpuhsl 12h aosc2 74h cpuhsh 13h aosc3 76h memar_at 1 4h aos c4 7 8h memhha_ at 1 6h aos c5 7 ah memhea_ at 1 8h aos c6 7 ch (4) configuration shasgn 1ch aosc7 7eh hhasgn 1eh (5) cpu search cpuinpl 80h cut0l 20h cpuinph 81h cut0h 21h cpumaskl 82h cut1l 22h cpumaskh 83h cut1h 23h cpusrs 84h ss0l 28h cpuinp2l 86h ss0h 29h cpuinp2h 87h ss1l 2ah cpumask2l 88h ss1h 2bh cpumask2h 89h cs0 30h cpusrs2 8ah cs1 32h (6) table s tatus hstat 90h cs2 34h estat 92h cs3 36h hhal 94h cs4 38h hhah 95h cs5 3ah heal 96h cs6 3ch heah 97h cs7 3eh sh 98h mask0l 40h cmp0l a0h mask0h 41h cmp0h a1h mask1l 42h cmp1l a2h mask1h 43h cmp1h a3h mask2l 44h cmp2l a4h mask2h 45h cmp2h a5h mask3l 46h cmp3l a6h mask3h 47h cmp3h a7h mask4l 48h cmp4l a8h mask4h 49h cmp4h a9h mask5l 4ah cmp5l aah mask5h 4bh cmp5h abh mask6l 4ch cmp6l ach mask6h 4dh cmp6h adh mask7l 4eh cmp7l aeh mask7h 4fh cmp7h afh
13-4 address processor ke5b256b1 13.3 register bit maps (1) command register group com (command register) add<7:0> = 00h each command is executed by writing the op-code in the eight bits of the lsb side (cc<7:0>) of this register. see chapter 12 for details of command op-code/function/ex- ecution condition. this register is only allowed to write. cc7 cc6 cc5 cc4 cc3 cc2 cc1 cc0 lsb msb 1514131211109876543210 bits 7 - 0 name cc<7:0> function op-code (8-bit) after rst_(srst) unknown
13-5 address processor ke5b256b1 (2) control status register cntl (control) register add<7:0> = (03h, 02h) this 32-bit register stores any information for the basic device setting. it is addressed into two 16-bit registers (the cntll register and the cntlh register). write the value (number of segments in one entry - 1) into the ww<2:0> bits according to the table configuration. the wp bit indicates the polarity of the wr pulse and the iw<1:0> bit indicates the input port width. the ea and eaoff bits indicate the relation of the endian. the busy bit indicates a change in the timing of the ipbusy_/ opact_ and opbust_/ipact_ signals. the ias, oas, ia<2:0>, and oa<2:0> bits are used to select the ip/op active channel. the ipns, ipn<2:0>, opn<2:0>, and opsn<2:0> bits are used to indicate the start sequence number. this register can be always read, but can be written only when there is no access from the input port or the output port. lsb msb cntlh cntlh 1514131211109876543210 oas ias ea wp iw1 iw0 ww2 ww1 ww0 oa2 oa1 oa0 ia2 ia1 ia0 busy eaoff opn2 ipns opn1 opn0 ipn2 ipn1 ipn0 opsn2opsn1opsn0 bits name function after rst_(srst) busy defines changing timing of thes e s ignals (ip b us y_ / o p ac t_ & o p b us y_ / ip ac t_ ) 15 0 at the start of the sequence these signals change 0 at the fis rt edge of the wr, rd_s ignal. at the 1 end of the sequence these signals change at the second edge of the wr, rd_signals. thes e s ignals always change at the firs t edge of the wr, rd_signal. eaoff endian function on/off 14 0 endian function on 0 1 endian function off *1 (fixed upper or lower side) ipns ip start sequence number selection method 1 2 0 indi c ate d by pi n (is nm<2 :0 >pi n s ) 0 1 indicated by register (ipn<2:0>bit) 10 - 8 opsn<2:0> *2 op start sub-sequence number 000 6 - 4 opn<2:0> *2 op start sequence number 000 2 - 0 ipn<2:0> *3 ip start sequence number 000
13-6 address processor ke5b256b1 *1 when the ea bit is set to "0," the upper side is fixed. when the ea bit is set to "1," the lower side is fixed. *2 this op start sequence number/start sub-sequence number is used when the opns pin is high level in the sequence pointer reset. *3 when the method for the ip start sequence number selection is the hardware channel selection, what is written here is ignored. the read data shows se- quence number which is selected by the isnm<2:0> bits. *4 the value (number of segment in one entry - 1) should be written into the ww<2:0> bit. in the case of a three-segment structure, the value is "010," and in case of an eight-segment structure, the value is "111." *5 in the case of the hardware channel selection, the written data here is ignored. the read data shows the channel which is determined by the opch pin. *6 in the case of the hardware channel selection, the written data here is ignored. the read data shows the channel which is determined by the ipch pin. bit name function after rst_(srst) oas op active channel s election method 14 0 software chnnel selection 0 1 hardware channel selection las ip active channel s election method 13 0 software chnnel selection 0 1 hardware channel selection ea endi an fl ag 12 0 big (16 bits of msb s ide firs t) 0 1 little (16 bits of lsb s ide firs t) wp polarity of wr 11 0 negative pulse 0 1 positive pulse iw1 iw0 input port width 10 - 9 0 0 32 bits 00 0 1 16 bits 1 0 8 bits 8 - 6 ww<2:0> *4 maximum segment number in one entry 000 oa2 oa1 oa0 *5 op active channel 5 - 3 0 0 0 a 0 00 0 0 1 b others reserved ia2 ia1 ia0 *6 ip active channel 2 - 0 0 0 0 a 0 00 0 0 1 b others reserved
13-7 address processor ke5b256b1 devid (device id) register add<7:0> = 04h this register stores the number of each device (device id) for the operation of cascaded systems. it is necessary to access this register and to set the device id for each device in a cascaded system after each device reset operation. the ld bit of the last device must be unique in the cas- caded system. the ld bit is set to "1" when a low pulse is given to the rst_ pin, or the srst command is issued. it is not necessary to write the ld bit in a single device sys- tem, but the ld bit must be set to "1" if the device id is re-written. this register is allowed to read/write only in the devid mode. msb lsb ld di4 di3 di2 di1 di0 1514131211109876543210 bits name function after rst_(srst) ld las t device flag 15 0 not last device 1 1 last device 4 - 0 di<4:0> device id 00000
13-8 address processor ke5b256b1 devstat (device status) register add<7:0> = 06h this register stores nine kinds of status information (bits to be accessed in the next read/write cycle, append re- sult flag, ip sequence number, op sequence number, op mode flag, cpu mode flag, tc sub-mode flag, and maxi- mum segment number in one entry) during operation. it is possible to confirm the state of operation by reading out the contents of this register. this register is allowed to read in all modes. nap as os2 os1 os0 opf is2 is1 is0 ipf cpf tcf lsb msb 1514131211109876543210 ww2 ww1 ww0 bits name function after rst_(srst) nap bits to be accessed in next read/write cycle 1 5 0 1 6 bits of ls b s ide in next read/write cycle 1 1 1 6 bits of ms b s ide in next read/write cycle as append result flag 14 0 append was invalid 0 1 append was valid 12 - 10 os<2:0> *1 op sequence number 000 opf *2 op mode flag 0not op mode 9 (now not op sequence) 1op mode (now op sequence) 8 - 6 is<2:0> *1 ip sequence number 000 ipf *3 ip mode fl ag 0not ip mode 5 (now not ip sequence) 0 1ip mode (now ip sequence)
13-9 address processor ke5b256b1 *1 the is/os bit shows the number of the ip/op se- quence executed during the sequence. *2 in the case of internal arbitration (sp/tp_pin is pulled down), the opf bit shows whether the mode of the device is the op mode or not. on the other hand, in case of external arbitration (sp/tp_ pin is pulled up), the opf bit shows whether the op mode is running or not. *3 the ipf bit shows whether the mode of the device is the ip mode or not in the case of internal arbitration (sp/tp_ pin is pulled down). on the other hand, in case of external arbitration (sp/tp_ pin is pulled up), the ipf bit shows whether the ip mode is running or not. *4 the cpf bit shows whether the mode of the device is the cpu mode or not in the case of internal arbitra- tion (sp/tp_ pin is pulled down). on the other hand, in case of external arbitration (sp/tp_ pin is pulled up), the cpf bit is "1." *5 the value defined in the cntl register can be read via ww<2:0> bits. bits name function after rst_(srst) cpf *4 cpu mode flag 4 0 not cpu mode 1 1cpu mode 3 - 1 ww<2:0> *5 maximum segment number in one entry 000 tcf tc s ub-mode fl ag 0 0 not tc s ub-mode 1 1 tc s ub-mode
13-10 address processor ke5b256b1 (3) memory r/w register group devsel (device select) register add<7:0> = 08h this register selects and accesses specific devices (device select) in a cascaded system. the br bit is set to "1," which means accessing all devices (broadcast), immedi- ately after the device reset operation. therefore, it is nec- essary to write "br=0" (not broadcast) and the device id which users wish to select in the ds<4:0> bits in this regis- ter when accessing only one specific device. this register is allowed to read/write in all modes. msb lsb br ds4 ds3 ds2 ds1 ds0 1514131211109876543210 bits name function after rst_(srst) br broadcas t flag 15 0 not broadcas t 1 1 broadcas t 4 - 0 ds<4:0> device id to be accessed 00000
13-11 address processor ke5b256b1 ar (address) register add<7:0> = 0ah this register specifies the absolute address in accessing the cam by the memar register. the data written in this register (0000h ~ 1fffh) is the absolute address of the cam to be accessed. it is possible to read/write the stored data of the cam specified by the absolute address by the read/write operation of the memar register after writ- ing the absolute address in this register. this register is al- lowed to read/write in all modes. lsb msb 1514131211109876543210 ar12 ar11 ar10 ar9 ar8 ar7 ar6 ar5 ar4 ar3 ar2 ar1 ar0 bits name function after rst_(srst) 12 - 0 ar<12:0> absolute address of the cam table 0000000000000
13-12 address processor ke5b256b1 memar (memory_ar) register add<7:0> = 0ch this 16-bit register operates as a port for accessing the ab- solute address of the cam indicated by the ar register. note that the bit map of this register is different in the tc sub-mode from the other modes. in accessing other than the tc sub-mode, access to 32-bit segment data in the cam table is limited to either the upper 16 bits or the lower 16 bits. the endian function controls which side is accessed. furthermore, this register can only be accessed without access from the input port or the output port. eb bb sg2 sg1 sg0 lsb msb read in tc sub-mode bb sg2 sg1 sg0 1514131211109876543210 write in tc sub-mode not in tc sub-mode (access to upper 16 bits) not in tc sub-mode (access to lower 16 bits) ma31 ma30 ma29 ma28 ma27 ma26 ma25 ma24 ma23 ma22 ma21 ma20 ma19 ma18 ma17 ma16 ma15 ma14 ma13 ma12 ma11 ma10 ma9 ma8 ma7 ma6 ma5 ma4 ma3 ma2 ma1 ma0 bits name function after rst_(srst) eb empty bit of tc data 40 not empty 1 1 empty bb boundary bit of tc data 3 0 not boun dar y unk n own 1 boundary 2 - 0 sg<2:0> segment number of tc data unknown 15 - 0 ma<31:16> segment data indicated by the ar register unknown (uppe r 1 6 bi ts ) 15 - 0 ma<15:0> segment data indicated by the ar register unknown (lower 16 bits)
13-13 address processor ke5b256b1 memhha (memory_hha) register add<7:0> = 0eh this register operates as a port for accessing addresses made by adding the entry address indicated by the hha register and the segment number specified by the cpuhs register. when accessing from the cpu port, either the upper 16 bits or the lower 16 bits of 32 bits in the cam table can be accessed. the endian function controls which side is accessed. furthermore, this register can only be ac- cessed without access from the input port or the output port. when reading this register as a search result by the op se- quence, 32-bit mh<31:0> bits are output on the od<31:0> bus. 1514131211109876543210 access to upper 16bits access to lower 16bits mh31 mh30 mh29 mh28 mh27 mh26 mh25 mh24 mh23 mh22 mh21 mh20 mh19 mh18 mh17 mh16 mh15 mh14 mh13 mh12 mh11 mh10 mh9 mh8 mh7 mh6 mh5 mh4 mh3 mh2 mh1 mh0 msb lsb bits name function after rst_(srst) 15 - 0 mh<31:16> segment data of entry indicated by unknown the hha register (upper 16 bits) 15 - 0 mh<15:0> segment data of entry indicated by unknown the hha register (lower 16 bits)
13-14 address processor ke5b256b1 memhea (memory_hea) register add<7:0> = 10h this register operates as a port for accessing addresses made by adding the entry address indicated by the hea register and the segment number specified by the cpuhs register. when accessing from the cpu port, either the upper 16 bits or the lower 16 bits of 32 bits in the cam table can be accessed. the endian function controls which side is accessed. furthermore, this register can only be ac- cessed without access from the input port or the output port. 1514131211109876543210 access to upper 16bits access to lower 16bits me31 me30 me29 me28 me27 me26 me25 me24 me23 me22 me21 me20 me19 me18 me17 me16 me15 me14 me13 me12 me11 me10 me9 me8 me7 me6 me5 me4 me3 me2 me1 me0 msb lsb bits name function after rst_(srst) 15 - 0 me<31:16> segment data of entry indicated by unknown the hea register (upper 16 bits) 15 - 0 me<15:0> segment data of entry indicated by unknown the hea register (lower 16 bits)
13-15 address processor ke5b256b1 cpuhs (cpu hha/hea segment) register add<7:0> = (13h, 12h) this 32-bit register indicates the method of the hha/hea register automatic increment, the method of the memhha/memhea register automatic increment, the segment number of the memhha/memhea, the method of stamp command automatic increment, the method of stamp command automatic swiop, and the method of append command automatic swiop. this reg- ister is addressed by dividing two 16-bit registers (the cpuhsh register, and the cpuhsl register). the method of the hha/hea register automatic incre- ment is indicated by the hhi/hei bits. the method of the memhha/memhea register auto- matic increment is indicated by the hm<1:0>/em<1:0> bits. in the case of a fixed segment, the segment number for access is indicated by hfs<2:0>/efs<2:0> bits. user can read the hs<2:0>/es<2:0> bits to confirm the seg- ment number for next access. when executing the stmp_hh/stmp_he commands, set hm<1:0>/em<1:0> to "00," and indicate the segment to be stamped with the hfs<2:0>/efs<2:0> bits. and when executing the (stmp_hh, stmp2_hh)/ (stmp_he, stmp2_he) command, the method of the hha/hea automatic increment is indicated by the shi/ sei bits. the stm/apm bit indicates whether the automatic swiop function of all stamp commands (stmp_ar, stmp_hh, stmp_he, stmp2_ar, stmp2_hh, stmp2_he) and of all append commands is enabled or not. bits name function after rst_(srst) apm append command automati c s wiop 5 0 automatic swiop disable 0 1 automatic swiop enable s tm s tamp command automati c s wiop 4 0 automatic swiop disable 0 1 automatic swiop enable sei stmp_he, stmp2_he command 3 automatic increment 0 0 increment 1 no increment shi stmp_hh, stmp2_hh command 2 automatic increment 0 0 increment 1 no increment cpuhsh pam stm sei shi hei hhi msb lsb hs1 1514131211109876543210 cpuhsl es2 es1 es0 em1 em0 efs2 efs1 efs0 hs2 hs0 hm1 hm0 hf2 hf0 hf1
13-16 address processor ke5b256b1 *1 the increment operation is executed by accessing the heal register. (the operation is not executed by ac- cessing the heah register.) *2 the increment operation is executed by accessing the hhal register. (the operation is not executed by ac- cessing the hhah register.) *3 when executing the stmp_he command, set the em<1:0> bits to "00." if the bits are not set to "00," the stmp_he command is not executed. on the other hand, execution of the stmp2_he command is not re- lated to the em<1:0> bits. *4 when executing the stmp_he command, the seg- ment to be stamped, which is indicated by the hea register, is determined by the efs<2:0> bits. on the other hand, the segment to be stamped is determined by the cg<2:0> bits of the cpusrs2 register. be careful of the difference in segment indicating the methods of both commands. *5 when executing the stmp_hh command, set the hm<1:0> bits to "00." if the bits are not set to "00," the stmp_hh command is not executed. on the other hand, execution of the stmp2_hh command is not related to the hm<1:0> bits. *6 when executing the stmp_hh command, the seg- ment to be stamped, which is indicated by the hha register, is determined by the hfs<2:0> bits. on the other hand, the segment to be stamped is determined by the cg<2:0> bits of the cpusrs2 register. be careful the difference in segment indicating the methods of both commands. bits name function after rst_(srst) hei *1 hea register automatic increment 1 0 increment 0 1 no increment hhi *2 hha register automatic increment 0 0 increment 0 1 no increment 15 - 13 es<2:0> memhea regis ter 000 segment number for next access em1 em0 memhea register automatic increment 0 0 *3 no increment segment number is incremental. entry number 12 - 11 0 1 is fixed. 00 entry number is incremental. segment number 1 0 is fixed. 1 1 segment number and entry number are incremental. 10 - 8 efs<2:0> *4 fixed segment number (memhea register) 000 7 - 5 hs<2:0> memhha register 000 segment number for next access hm1 hm0 memhha register automatic increment 0 0 *5 no increment segment number is incremental. entry number 4 - 3 0 1 is fixed. 0 0 entry number is incremental. segment number 1 0 is fixed. 1 1 segment number and entry number are incremental. 2 - 0 hfs<2:0> *6 fixed segment number (memhha register) 000
13-17 address processor ke5b256b1 memar_at (memory_ar attribute) register add<7:0> = 14h this register reads/writes the access bit indicated by the ar register , and reads the empty bit. beforehand, write the desired entry address (the start address of the cam ad- dress) into the ar register. only this register can be ac- cessed when there is no access from the input port or the output port. bits name function after rst_(srst) ab acces s bit 5 0 no past career 0 1 past career eb empt y b i t 4 0 no empty (valid) 1 1empty msb lsb ab eb 1514131211109876543210
13-18 address processor ke5b256b1 memhha_at (memory_hha attribute) register add<7:0> = 16h this register reads/writes the access bit indicated by the hha register , and reads the empty bit. beforehand, write the desired entry address (the start address of the cam ad- dress) into the hha register. only this register can be ac- cessed when there is no access from the input port or the output port. bits name function after rst_(srst) ab acces s bit 5 0 no past career 0 1 past career eb empt y b i t 4 0 no empty (valid) 1 1empty msb lsb ab eb 1514131211109876543210
13-19 address processor ke5b256b1 memhea_at (memory_hea attribute) register add<7:0> = 18h this register reads/writes the access bit indicated by the hea register , and reads the empty bit. beforehand, write the desired entry address (the start address of the cam ad- dress) into the hea register. only this register can be ac- cessed when there is no access from the input port or the output port. bits name function after rst_(srst) ab acces s bit 5 0 no past career 0 1 past career eb empt y b i t 4 0 no empty (valid) 1 1empty msb lsb ab eb 1514131211109876543210
13-20 address processor ke5b256b1 (4) configuration register group shasgn (sequence hit flag assignment) register add<7:0> = 1ch this 16-bit register determines the number of the step at which the search results of the ip sequence are to be out- put. the upper eight bits a1<7:0> of 16 bits correspond to the ip sequence number from 7 to 0. by setting one bit of these eight bits to "1," the result of the ip sequence number which corresponds to this bit is output on the sh1_ pin. two or more bits can not be set to "1." the lower eight bits a0<7:0> of 16 bits correspond to the steps ip sequence number from 7 to 0, and the result is output in the sh0_ pin. the other items are the same as the upper eight bits. msb lsb a17 a16 a15 a14 a13 a12 a11 a10 a07 a06 a05 a04 a03 a02 a01 a00 1514131211109 87 65 4321 0 bits name function after rst_(srst) 15 - 8 a1<7:0> defines the ip sequence number of which the 00000000 res ult s hould be output on sh1_ . 7 - 0 a0<7:0> defines the ip sequence number of which the 00000000 res ult s hould be output on sh0_ .
13-21 address processor ke5b256b1 hhasgn (hha automatic output assignment) register add<7:0> = 1eh this register indicates enabling of the hha automatic out- put function in the ip sequence. ipha<7:0> bits corre- spond to the ip sequence numbers of 7 to 0 in the a chan- nel. the automatic hha output is executed in the se- quence number which correspond to "1" set bits of this reg- ister. iphb<7:0> bits are prepared for the b channel. the method of setting is the same as the ipha<7:0> bits. in a cascaded system users need to be careful of the sequence number, which indicates the hha output, in order to pre- vent hha output collision on the od<31:0> bus. iphb7 iphb6 iphb5 iphb4 iphb3 iphb2 iphb1 iphb0 ipha7 ipha6 ipha5 ipha4 ipha3 ipha2 ipha1 ipha0 msb lsb 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bits name function after rst_(srst) 15 - 8 iphb<7:0> defines the hha automatic output sequence 00000000 number in the ip sequence using the bch 7 - 0 ipha<7:0> defines the hha automatic output sequence 00000000 number in the ip sequence using the ach
13-22 address processor ke5b256b1 cut (cut) register add<7:0> = (21h, 20h), (23h, 22h) this 64-bit register determines what number of the 64 blocks of the input data stream from the input port should be acquired. it is divided by 16 bits, and is addressed as the (cut0h, cut0l), (cut1h, cut1l). each bit ct<63:0> corresponds to one of the blocks from the 63rd to the 0 block of the input data stream. by setting the bit of the block number to "1," the block is input into the device. the registers for the a channel and the b channel are as- signed the same address as the other configuration regis- ters. the active channel is not allowed to access. the inac- tive channel is allowed to access in all modes. msb cut1h ct63 lsb 1514131211109876543210 cut0l cut1l cut0h ct62 ct61 ct60 ct59 ct58 ct57 ct56 ct55 ct54 ct53 ct52 ct51 ct50 ct49 ct48 ct47 ct46 ct45 ct44 ct43 ct42 ct41 ct40 ct39 ct38 ct37 ct36 ct35 ct34 ct33 ct32 ct31 ct30 ct29 ct28 ct27 ct26 ct25 ct24 ct23 ct22 ct21 ct20 ct19 ct18 ct17 ct16 ct15 ct14 ct13 ct12 ct11 ct10 ct9 ct8 ct7 ct6 ct5 ct4 ct3 ct2 ct1 ct0 bits name function after rst_(srst) ct<63 :0> cut flag of id<31 :0> 15 - 0 0 not cut (dis cards data) unknown 1 cut (acquires data)
13-23 address processor ke5b256b1 ss (search start) register add<7:0> = (29h, 28h), (2bh, 2ah) this 64-bit register determines the point of input port data acquisition, which is defined by the cut register. it is di- vided by 16 bits, and is addressed as the (ss0h, ss0l), (ss1h, ss1l). each bit ss<63:0> corresponds to one of the blocks from the 63rd to the 0 block of the input data stream. by setting the bit of the block number to "1," the search operation is executed. as the number of ip se- quence step is eight, it is possible to set up to a maximum of eight bits to "1." the registers for the a channel and the b channel are assigned the same address as the other con- figuration registers. the active channel is not allowed to access. the inactive channel is allowed to access in all modes. msb ss1h ss63 lsb 1514131211109876543210 ss0l ss1l ss0h ss62 ss61 ss60 ss59 ss58 ss57 ss56 ss55 ss54 ss53 ss52 ss51 ss50 ss49 ss48 ss47 ss46 ss45 ss44 ss43 ss42 ss41 ss40 ss39 ss38 ss37 ss36 ss35 ss34 ss33 ss32 ss31 ss30 ss29 ss28 ss27 ss26 ss25 ss24 ss23 ss22 ss21 ss20 ss19 ss18 ss17 ss16 ss15 ss14 ss13 ss12 ss11 ss10 ss9 ss8 ss7 ss6 ss5 ss4 ss3 ss2 ss1 ss0 bits name function after rst_(srst) ss<63:0> search start flag 15 - 0 0 no s earch unknown 1 search
13-24 address processor ke5b256b1 *1 must be set from 0 to (segment number in one entry -1) value. cs (channel sequence) register add<7:0> = 30h, 32h, 34h, 36h, 38h, 3ah, 3ch, 3eh this register determines how to format id<31:0> and how to search in the ip search operation. it is prepared for each of the 8 search steps of the ip sequence. each of the eight registers is given an address from cs0 to cs7. the registers for the a channel and the b channel are as- signed the same address as the other configuration regis- ters. the active channel is not allowed to access. the inac- tive channel is allowed to access in all modes. msb lsb eos ig2 ig1 ig0 ish iac sw1 sw0 1514131211109876543210 bits name function after rst_(srst) eos end-of-sequence flag of ip 15 0 not end of ip sequence unknown 1 end of ip sequence 14 - 12 ig<2:0> *1 ip search segment number unknown ish search head flag in ip search 0 not s earch head 3 (and search with previous search) unknown 1 search head (not and search with previous search) iac acces s bit set flag in ip s earch 2 0 not set access bit unknown 1 set access bit sw1 sw2 search window set 0 0 0-byte s hift 1 - 0 0 1 1-byte shift unknown 1 0 2-byte s hift 1 1 3-byte s hift
13-25 address processor ke5b256b1 mask (mask) register add<7:0> = (41h, 40h), (43h, 42h), (45h, 44h), (47h, 46h), (49h, 48h), (4bh, 4ah), (4dh, 4ch), (4fh, 4eh) this register sets the mask pattern with a unit of one bit in the ip search operation. it is prepared for each of the 8 search steps of the ip sequence. each of the eight registers is given an address from mask0 to mask7. the regis- ters for the a channel and the b channel are assigned the same address as the other configuration registers. the ac- tive channel is not allowed to access. the inactive channel is allowed to access in all modes. 1514131211109876543210 maskl maskh mk31 mk30 mk29 mk28 mk27 mk26 mk25 mk24 mk23 mk22 mk21 mk20 mk19 mk18 mk17 mk16 mk15 mk14 mk13 mk12 mk11 mk10 mk9 mk8 mk7 mk6 mk5 mk4 mk3 mk2 mk1 mk0 msb lsb bits name function after rst_(srst) mk<31:0> mas k flag for 32-bit key data 15 - 0 0 no mask unknown 1mask
13-26 address processor ke5b256b1 *1 be sure to set "1" when the result is the hstat or cmp register. *2 five kinds of register (hstat, cpm, hha, memhha, hha & memhha) can be indicated for output. aoc (automatic output control) register add<7:0> = 60h, 62h, 64h, 66h, 68h, 6ah, 6ch, 6eh when reading in the op sequence, this register determines how to read the search results. it is prepared for each of the 8 search steps of the ip sequence. each of the eight regis- ters is given an address from aoc0 to aoc7. when user reads 16-bit divided registers like the hha or cmp regis- ters, write the or<7:0> bits of the lower side address. the registers for the a channel and the b channel are assigned the same address as the other configuration registers. the active channel is not allowed to access. the inactive chan- nel is allowed to access in all modes. msb lsb eos mx1 mx0 oa or7 or6 or5 or4 or3 or2 or1 or0 1514131211109876543210 bits name function after rst_(srst) eos end-of-sequence flag of op sequence 15 0 not end of op s equence unknown 1 end of op s equence mx1 mx2 method of mixing hstat regis ter and od<31:22> 0 0 no mixing 14 - 13 0 1 outputs hstat<11:6> on od<27:22> unknown 1 0 outputs hstat<15:12> on od<31:28> 1 1 outputs hstat<15:6> on od<31:22> oa *1 one/all_flag 12 0 outputs al l hha/ memhha unk nown 1 o ut pu t s on e hha / memhha 7 - 0 or<7:0> *2 register designation to od<31:0> unknown
13-27 address processor ke5b256b1 aosc (automatic output sub control) register add<7:0> = 70h, 72h, 74h, 76h, 78h, 7ah, 7ch, 7eh this register determines the segment of an hha entry to be output and the sequence of such segments, when the memhha register or hha&memhha register is speci- fied in the or<7:0> of the aoc register. it consists of 8 kinds (aosc0 ~ aosc7) of registers, so a maximum of eight segments are indicated. each register corresponds to the op sub-sequence number. mixing with the hstat register takes priority over specification of the aoc regis- ters. the registers for the a channel and the b channel are assigned the same address as the other configuration regis- ters. the active channel is not allowed to access. the inac- tive channel is allowed to access in all modes. 1514131211109876543210 msb eoss mxs1 mxs0 os2 os1 os0 lsb bits name function after rst_(srst) eoss end-of-sub-sequence flag of op 1 5 0 not e nd of s u b-s e que n c e unk n own 1 end of sub-sequence mxs 1 mxs 2 method of mixing hs at regis ter and od<31 :22 > 0 0 not mixing 14 - 13 0 1 outputs hs tat<11 :6> on od<2 7:2 2> unk nown 1 0 outputs hstat<15:12> on od<31:28> 1 1 outputs hs tat<15 :6> on od<3 1:2 2> 2 - 0 os<2:0> outputs s egment number unknown
13-28 address processor ke5b256b1 (5) cpu search register group cpuinp (cpu input data) register add<7:0> = (81h, 80h) this 32-bit register sets 32-bit key data in the search opera- tion with the srch command via the cpu port. it is di- vided into units of 16 bits, each of which is given an ad- dress of cpuinph or cpuinpl. when one of the stmp_ar, stmp_hh, or stmp_he commands is ex- ecuted, the data in this register is written into the desired segment in the cam. 1514131211109876543210 cpuinpl cpuinph ci31 ci30 ci29 ci28 ci27 ci26 ci25 ci24 ci23 ci22 ci21 ci20 ci19 ci18 ci17 ci16 ci15 ci14 ci13 ci12 ci11 ci10 ci9 ci8 ci7 ci6 ci5 ci4 ci3 ci2 ci1 ci0 msb lsb bits name function after rst_(srst) 15 - 0 ci<31:0> 32-bit key data from the cpu port unknown
13-29 address processor ke5b256b1 cpumask (cpu mask) register add<7:0> = (83h, 82h) this 32-bit register sets mask patterns with a unit of one bit in search operations via the cpu port. it is divided into units of 16 bits, each of which is given an address of the cpumaskh or cpumaskl. when one of the stmp_ar, stmp_hh, or stmp_he commands is ex- ecuted, the bits to be masked are determined by this regis- ter. 1514131211109876543210 cpumaskl cpumaskh cm31 cm30 cm29 cm28 cm27 cm26 cm25 cm24 cm23 cm22 cm21 cm20 cm19 cm18 cm17 cm16 cm15 cm14 cm13 cm12 cm11 cm10 cm9 cm8 cm7 cm6 cm5 cm4 cm3 cm2 cm1 cm0 msb lsb bits name function after rst_(srst) cm<31:0> mask flag for 32-bit key data for cpu search 15 - 0 0 no mask unknown 1 mas k
13-30 address processor ke5b256b1 cpusrs (cpu search segment) register add<7:0> = 84h this register determines whether the access bits are set or not, and whether the search head is accessed or not, along with the segment number to be searched in the cpu search. *1 must be set from 0 to (segment number in one entry - 1) value. msb lsb ac ad cg2 cg1 cg0 1514131211109876543210 bits name function after rst_(srst) ac access bit set flag in cpu search 4 0 not set access bit unknown 1 set access bit ad search head flag in cpu s earch 0 not s earch head 3 (and search with previous search) unknown 1 search head (not and search with previous search) 2 - 0 cg<2:0> *1 cpu search segment number unknown
13-31 address processor ke5b256b1 cpuinp2 (cpu input data 2) register add<7:0> = (87h, 86h) this 32-bit register sets 32-bit key data in the search opera- tion with the srch2 command via the cpu port. it is di- vided into units of 16 bits, each of which is given an ad- dress of cpuinp2h or cpuin2pl. when one of the stmp2_ar, stmp2_hh, or stmp2_he commands is executed, the data in this register is written into the desired segment in the cam. the bit map of the register is the same as the cpuinp register. 1514131211109876543210 cpuinp2l cpuinp2h ci31 ci30 ci29 ci28 ci27 ci26 ci25 ci24 ci23 ci22 ci21 ci20 ci19 ci18 ci17 ci16 ci15 ci14 ci13 ci12 ci11 ci10 ci9 ci8 ci7 ci6 ci5 ci4 ci3 ci2 ci1 ci0 msb lsb bits name function after rst_(srst) 15 - 0 ci<31:0> 32-bit key data from the cpu port unknown
13-32 address processor ke5b256b1 cpumask2 (cpu mask 2) register add<7:0> = (89h, 88h) this 32-bit register sets mask patterns with a unit of one bit in search operations via the cpu port. it is divided into units of 16 bits, each of which is given an address of cpumask2h or cpumask2l. when one of the stmp2_ar, stmp2_hh, or stmp2_he commands is executed, the bits to be masked are determined by this reg- ister. the bit map of the register is the same as the cpumask register. 1514131211109876543210 cpumask2l cpumask2h cm31 cm30 cm29 cm28 cm27 cm26 cm25 cm24 cm23 cm22 cm21 cm20 cm19 cm18 cm17 cm16 cm15 cm14 cm13 cm12 cm11 cm10 cm9 cm8 cm7 cm6 cm5 cm4 cm3 cm2 cm1 cm0 msb lsb bits name function after rst_(srst) cm<31:0> mas k flag for 32-bit key data for cpu search 15 - 0 0 no mask unknown 1mask
13-33 address processor ke5b256b1 cpusrs2 (cpu search segment 2) register add<7:0> = 8ah this register determines whether access bits are set or not, and whether the search head is accessed or not, in addition to and the segment number to be searched in the cpusearch. the bit map of the register is the same as the cpusrs register. however, it is different from the cpusrs register in that this register indicates the segment number to be stamped in executing the stmp2_hh or stmp2_he commands. *1 must be set from 0 to (segment number in one entry - 1) value. *2 the segment to be stamped is determined by cg<2:0> bits in executing the stmp2_hh or stmp2_he commands. the stmp_hh and stmp_he commands, are not related. msb lsb ac ad cg2 cg1 cg0 1514131211109876543210 bits name function after rst_(srst) ac access bit set flag in cpu search 4 0 not set access bit unknown 1 set access bit ad search head flag in cpu s earch 3 0 not s earch head unknown (and search with previous search) 1 search head (not and search with previous search) 2 - 0 cg<2:0> *1 cpu search segment number unknown
13-34 address processor ke5b256b1 (6) table status register group hstat (hit status) register add<7:0> = 90h this register stores the results of searching via the input port or the cpu port, and active channel information. it is possible to confirm the result of a search by reading this register. this register can be not only output from the cpu port, but also can be output from the output port. in this case the data is output on the od<15:0> of the 32-bit od<31:0> bus. and when a mixed output is indicated in the op sequence, the <15:6> bit of the hstat register is output on od<31:22> according to the indication. this register stores information which is conveyed among devices, such as a hit in the system, and multiple hits in the system. the information on the last device thus becomes precise information of the system. therefore, the last device outputs the information in the broad- cast method. this register is allowed only to read in all modes. msb lsb syh sym ht mh oa2 oa1 oa0 ia2 ia1 ia0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bits name function after rst_(srst) syh sys tem hit flag 15 0 no hit in a cas caded s ys tem unk nown 1 hit in a cascaded system s ym s ys tem multi-hit flag 14 0 no multi-hit in a cas caded s ys tem unk nown 1 multi-hit in a cascaded system syh device hit flag 13 0 no hit in the device unknown 1 hit in the device mh device multi-hit flag 12 0 no multi-hit in the device unknown 1 multi-hit in the device oa2 oa1 oa0 op active channel 11 - 9 0 0 0 a 00 0 0 0 1 b others reserved ia2 ia1 ia0 ip active channel 8 - 6 0 0 0 a 000 0 0 1 b others reserved
13-35 address processor ke5b256b1 estat (empty status) register add<7:0> = 92h this register stores empty information of the cam table, and active channel information. it is possible to confirm the information regarding empty entries in the cam table by reading this register. this register also stores empty information in the system which is con- veyed among devices, as with the hstat register. therefore, the last device information becomes precise information for the system. the last device outputs the data in the broadcast method. this register is allowed only to read in all modes. msb lsb sye et oa2 oa1 oa0 ia2 ia1 ia0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bits name function after rst_(srst) s ye s ys tem empty flag 15 0 no empty entry (full) in a cas caded s ys tem unk nown 1 empty entry in a cascaded system et device empty flag 13 0 no empty entry (full) in the device unknown 1 empty entry in the device oa2 oa1 oa0 op active channel 11 - 9 0 0 0 a 00 0 0 0 1 b reserved reserved ia2 ia1 ia0 ip active channel 8 - 6 0 0 0 a 000 0 0 1 b reserved reserved
13-36 address processor ke5b256b1 hha (highest hit address) register add<7:0> = (95h, 94h) this register stores the entry address of the highest hit en- try, and its device id after a searching operation via the input port or the cpu port. the smaller the absolute ad- dress becomes, the higher its priority ranks; the higher the location of a device in a cascaded system is, the higher its priority ranks. this register is divided into the hhah and hhal registers. when reading with the op sequence, the hhah register is output on od<31:16>, and the hhal register is output on od<15:0> at the same time as 32-bit data. when the hv is "0," there is no hit entry, and the ha<12:0> bit is invalid. this register is allowed only to read in all modes. msb lsb hhah hv ld di4 di3 di2 di1 di0 hhal hv ha12 ha11 ha10 ha9 ha8 ha7 ha6 ha5 ha4 ha3 ha2 ha1 ha0 1514131211109876543210 bits name function after rst_(srst) hv hi g he s t hi t addr e s s v al i d fl ag 15 0 invalid unknown 1 valid ld las t device flag 14 0 not last device 1 1 last device 4 - 0 di<4:0> device id 00000 12 - 0 ha<12:0> highest hit address 0000000000000
13-37 address processor ke5b256b1 hea (highest empty address) register add<7:0> = (97h, 96h) this register stores the entry address of the highest empty entry and its device id. the smaller the absolute address becomes, the higher its priority ranks; the higher the loca- tion of a device in a cascaded system is, the higher its pri- ority ranks. this register is divided into heah and heal. in reading via the cpu port, this register can be read as heah and heal. when the ev is "0," there is no empty entry, and the he<12:0> bit is invalid. this register is allowed only to read in all modes. msb lsb heah ev ld di4 di3 di2 di1 di0 heal ev he12 he11 he10 he9 he8 he7 he6 he5 he4 he3 he2 he1 he0 1514131211109876543210 bits name function after rst_(srst) ev hig hes t empty addres s valid flag 15 0 invalid unknown 1 valid ld las t device flag 14 0 not last device 1 1 last device 4 - 0 di<4:0> device id 00000 12 - 0 he<12:0> highest empty address unknown
13-38 address processor ke5b256b1 sh (sequence hit result) register add<7:0> = 98h this register stores the ip sequence results of each device as the characteristic information of each device. each reg- ister sh<7:0> corresponds to the search results of each se- quence (no.7 - no.0). if the and search operation is de- fined in the ip sequence, the sh<7:0> corresponding to the sequence number shows the result of the and search of the previously executed sequence. this register is al- lowed to read in all modes only when the device has been selected. msb lsb sh7 sh6 sh5 sh4 sh3 sh2 sh1 sh0 1514131211109876543210 bi ts name functi on after rst_(srst) sh<7:0> search results at ip sequence number 7 - 0 0 no hit 00000000 1hit
13-39 address processor ke5b256b1 cmp (comparand) register add<7:0> = (a1h, a0h), (a3h, a2h), (a5h, a4h), (a7h, a6h), (a9h, a8h), (abh, aah), (adh, ach), (afh, aeh) this 32-bit register stores search key data used in the ip sequence. it is prepared for eight steps, which correspond to eight kinds of registers (cmp0 - cmp7). each is di- vided into two parts (16 bits each), and is addressed as (cmp0l, cmp0h) - (cmp7l, cmp7h). this register is allowed to read in the cpu mode from the cpu port. msb lsb cmph cp31 cp30 cp29 cp28 cp27 cp26 cp25 cp24 cp23 cp22 cp21 cp20 cp19 cp18 cp17 cp16 cmpl cp15 cp14 cp13 cp12 cp11 cp10 cp9 cp8 cp7 cp6 cp5 cp4 cp3 cp2 cp1 cp0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bits name function after rst_(srst) 15 - 0 cp<31:0> 32-bit key data us ed in ip s earch unknown
13-40 address processor ke5b256b1 *1 see table 12.2. *2 the write operation is executed for all devices. (it is not possible to specify the device.) table 13.4 conditions for accessing registers *3 it is possible to access only the device which has the devid priority. (it is not possible to specify the device.) 13.4 conditions for accessing registers com register name cntl devid devstat devsel ar memar memar_at memhha memhha_at memhea memhea_at cpuhs shasgn hhasgn cut ss cs mask aoc aosc cpuinp cpumask cpusrs cpuinp2 cpumask2 cpusrs2 hstat estat hha hea sh cmp broadcast write written device read outputting device device select write read access mode in the internal arbitration (sp/tp_=low) write read *1 *3 all devices all devices devid priority device no device all devices all devices all devices *4 hit priority device *5 empty priority device *9 all devices all devices all devices all devices no device no device no device no device no device no device last device devid priority device last device last device last device last device hit priority device *6 empty priority device *10 last device last device last device last device last device hit priority device *6 empty priority device *10 no device last device *1 *2 *3 *2 *2 *7 *11 *2 *2 *2 *2 *3 *8 *12 *1 cpu mode always devid sub-mode always always always cpu mode cpu mode cpu mode always always always (only inactive cannel) always always always always always cpu mode :allowed :allowed but not selectable :not allowed
13-41 address processor ke5b256b1 *4 the write operation is executed for all devices. in case the table configuration is in a cascaded system, use the broadcast write operation of the memar register, not the broadcast access. *5 the device which has the hit priority receives the data. (when there is no device which has the hit pri- ority, the write operation is not executed.) *6 when there is no device which has the hit priority in a cascaded system, the last device outputs invalid data. *7 when the selected device has no hit entry, the write operation is not executed. *8 when the selected device has no hit entry, the device outputs invalid data. *9 only the device which has the empty priority re- ceives data. (when there is no device which has the empty prior- ity, the write operation is not executed.) *10 when there is no device which has the empty prior- ity in a cascaded system, the last device outputs in- valid data. *11 when the selected device has no hit entry, the device outputs invalid data. *12 when the selected device has no empty entry, the device outputs invalid data.
14-1 address processor ke5b256b1 ? other pins except the sh0_ and sh1_ pins (open drain output) are 5v tolerant i/o pins. ? the sh0_ and sh1_ pins should be pulled up by 3.3 v power. ? the pulled down resister's value should be less than 30kohm when each pin is pulled down. 14. electrical characteristics 14.1 absolute maximum rating 14.2 operating range 14.3 dc characteristics item symbol standard condition unit note s upply voltage v dd - 0. 3 ~ 4 . 6 v input voltage v i - 0. 3 ~ 7. 3 v output voltage v o - 0. 3 ~ 7. 3 v - 0. 3 ~ v dd + 0. 3 v sh0_, sh1_ i/o voltag e v io - 0. 3 ~ 7 . 3 v s torag e temperature t s tg - 40 ~ + 1 25 c item s ymbol min. typ. max. unit supply voltage v dd 3 . 0 3 . 3 3 . 6 v ambient operating temperature t a 0 + 25 + 70 c item s ymb ol min. typ. max. unit condition input low voltage v il 0. 8 v input high voltage v ih 2. 0 v output low voltage v ol 0. 4 v i ol = 4 ma output high voltage v oh 2. 4 v i oh = - 4ma input leakage current i il - 70 a v in = gnd i ih 10 a v in = v dd output leakage current i oz - 10 10 a output is high impedance standby current i dds 450 a dynamic operating current i ddop 200 ma
14-2 address processor ke5b256b1 t a = 0 ~ 70 c, v dd = 3.3 v 0.3 v 14.4 ac characteristics *1 when the wr is a negative pulse. if the wr is a positive pulse, this parameter is the wr high pulse width. *2 when the wr is a negative pulse. if the wr is a positive pulse, this parameter is the wr low pulse width. *3 the sh0_ and sh1_ change in a defined sequence number. *4 when od<31:0> or dat<15:0> off delay is measured, a 400mv change from the loaded v oh /v ol level occurs. no. parameter min. max. unit note input port cycle 1 wr cycle time 80 ns 2wr width low 40 ns* 1 3 wr width high 20 ns * 2 4 id<31:0> setup time to wr 5 ns 5 id<31:0> hold time after wr 20 ns 6 ho_ valid from wr 70 ns 7 ho_ hold after wr 5 ns 8 sh0_, sh1_ valid from wr 70 ns * 3 9 po_ valid from wr 1 00 ns 10 po_ hold after wr 5 ns output port cycle 11 rd_ cycle time 80 ns 12 rd_ width low 60 ns 13 rd_ width high 20 ns 14 id<31:0> setup time to rd_ 10 ns 15 id<31:0> hold time after rd_ ns 16 rd_ low to od<31:0> active 55 ns 17 rd_ high to od<31:0> inactive 0 ns 18 rd_ low to ho_ active 70 ns 19 rd_ high to ho_ inactive 5 ns 20 rd_ low to po_ active 100 ns 21 rd_ high to po_ inactive 5 ns 22 oe_ low to od<31:0> active 20 ns 23 oe_ high to od<31:0> disable 15 ns * 4
14-3 address processor ke5b256b1 *5 in the case of operations requiring a hit priority decision (see table 9.7.1), hold time of the hi_ is necessary. *6 in cases when the hstat register is read, setup and hold time of the pi_ is necessary to be added to the hi_. *7 in the case of operations requiring empty priority decision (see table 9.7.1), setup and hold time of the fli_ is necessary. *8 in the case of operations which change an empty priority (see table 9.7.1), the flo_ changes. *9 in the case of operations which change a hit priority (see table 9.7.1), the ho_ and po_ change. no. parameter min. max. unit note cpu port write cycle 24 ce_ cycle time 80 ns 25 ce_ width low 60 ns 26 ce_ width high 20 ns 27 hi_, pi_, fli_ s etup time to ce_ 10 ns * 5, 6, 7 28 hi_, pi_, fli_ hold time after ce_ 5 ns * 5, 6, 7 29 dat<15:0> s etup time to ce_ 5 ns 30 dat<15:0> hold time after ce_ 10 ns 31 add<7:0> s etup time to ce_ 5 ns 32 add<7:0> hold time after ce_ 10 ns 33 r/w_ s etup time to ce_ 5 ns 34 r/w_ hold time to ce_ 10 ns 35 ce_ low to flo_ active 70 ns * 8 36 ce_ high to flo_ inactive 5 ns * 8 37 ce_ low to ho_ active 70 ns * 9 38 ce_ high to ho_ inactive 5 ns * 9 39 ce_ low to po_ active 100 ns * 9 40 ce_ high to po_ inactive 5 ns * 9 cpu port read cycle 24 ce_ cycle time 80 ns 25 ce_ width low 60 ns 26 ce_ width high 20 ns 27 hi_, pi_, fli_ s etup time to ce_ 10 ns *5, 6, 7 28 hi_, pi_, fli_ hold time after ce_ 5 ns *5, 6, 7 31 add<7:0> s etup time to ce_ 5 ns 32 add<7:0>hold taime after ce_ 10 ns 33 r/w_ s etup time to ce_ 5 ns 34 r/w_ hold time to ce_ 10 ns 35 ce_ low to flo_ active 70 ns * 8 36 ce_ high to flo_ inactive 5 ns * 8 37 ce_ low to ho_ active 70 ns * 9 38 ce_ high to ho_ inactive 5 ns * 9 39 ce_ low to po_ active 100 ns * 9 40 ce_ high to po_ inactive 5 ns * 9 41 ce_ low to dat<15:0> active 20 ns 42 dat<15:0> valid from ce_ 55 ns 43 ce_ high to dat<15:0> disable 5 15 ns * 4
14-4 address processor ke5b256b1 *10 in cases when the sp/tp_ is pulled down (internal arbitration), the rd_ pulses are ignored until the ip sequence is completed. *11 operations requiring hit priority decision (see table 9.7.1) or access to the cam table (see table 4.3.1) are neces- sary to be executed after the input port cycle is completed. *12 in cases when the sp/tp_ is pulled down (internal arbitration) access to the cam table (see table 4.3.1) can only be executed when the mode of device is the cpu mode. *13 in cases when the swiop command is used. *14 since the device has to be registered with the device id, and the table configuration must be executed immediately after the device reset operation with the rst_ pulse, the device is accessed from the cpu port with the ce_. (do not access the device from the input port or the output port with the wr or the rd_.) no. parameter min. max. unit note pulse to pulse 44 wr active rd_ low 80 ns * 10 45 wr inactive rd_ low 20 ns * 10 46 wr active ce_ low 80 ns * 11, 12 47 wr inactive ce_ low 20 ns * 11, 12 48 rd_ low to wr active 80 ns 4 9 rd_ high to wr active 2 0 ns 50 rd_ low to ce_ low 80 ns * 11, 12 51 rd_ high to ce_ low 20 ns * 11, 12 52 ce_ low to wr active 80 ns * 11, 12, 13 53 ce_ high to wr active 20 ns * 11, 12, 13 54 ce_ low to rd_ low 80 ns * 11, 12, 13 55 ce_ high to rd_ low 20 ns * 11, 12, 13 56 rst_ hgih to ce_ low 20 ns * 14 57 sqrst_ or ce_(ssqrst command) high to wr active 20 ns 5 8 wr active to sqrst_ or ce_ (ssqrst command) low 8 0 ns 59 wr inactive to sqrst_ or ce_ (ssqrst command) low 20 ns 60 sqrst_ or ce_(ssqrst command) high to rd_ low 20 ns 61 rd_ low to ce_(ssqrst command) low to rd_ low 80 ns 62 rd_ high to ce_(ssqrst command) low to rd_ low 20 ns
14-5 address processor ke5b256b1 *15 in cases when the sp/tp_ is pulled down (internal arbitration), both the ipbusy_/opact_ and opbusy_/ipact_ pins become low level with the srst command. this state indicates the mode of device is the cpu mode. in cases when the sp/tp_ is pulled up (external arbitration), both the ipbusy_/opact_ and opbusy_/ipact_ pins become high level with the srst command. *16 in cases when the sp/tp_ is pulled down (internal arbitration), both the ipbusy_/opact_ and opbusy_/ipact_ pins become high level with the swiop command. this state indicates that the mode of device is the iop mode. *17 in cases when the sp/tp_ is pulled down (internal arbitration), both the ipbusy_/opact_ and opbusy_/ipact_ pins become low level with the swcpup or swcpup_im command in the iop mode. this state indicates that the mode of device is the cpu mode. *18 in cases when the sp/tp_ is pulled up (external arbitration), the mode transition commands (swiop, swcpup, swcpup_im, swcpup_sqe) are not necessary. *19 in cases when the sp/tp_ is pulled down (internal arbitration), both the ipbusy_/opact_ and opbusy_/ipact_ pins become high level with the automatic swiop enabled and the stamp or append command execution. this state indicates that the mode of device is the iop mode. in cases when the sp/tp_ is pulled up (external arbitration), the automatic swiop function is not necessary to use. *20 in the ip sequence start, and the ip sequence end with the busy bit of the cntl register setting to "1." *21 in the ip sequence end with the busy bit of the cntl register setting to "0." *22 in the op sequence start, and the op sequence end with the busy bit of the cntl register setting to "1." *23 in the op sequence end with the busy bit of the cntl register setting to "0." no. parameter min. max. unit note trans ition of ipbus y_/opact_ and opbus y_/ipact_ 63 ce_ low to ipbusy_/opact_, opbusy_/ipact_ 40 ns * 15, 16, 17 trans ition time 18 64 ce_ high to ipbusy_/opact_, opbusy_/ipact_ 30 ns * 19 trans ition time 65 wr active to opbusy_/ipact_ trans ition time 30 ns * 20 66 wr inactive to opbusy_/ipact_ trans ition time 30 ns * 21 67 rd_ low to ipbusy_/opact_ transition time 30 ns * 22 68 rd_ high to ipbusy_/opact_ transition time 30 ns * 23 69 ce_(ssqrst command) high to opbusy_/ipact_ 30 ns trans ition time 70 ce_(ssqrst command) high to ipbusy_/opact_ 30 ns trans ition time
14-6 address processor ke5b256b1 *24 in cases when the busy bit of the cntl register is set to "0," cpu interrupt with the swcpup, swcpup_im, and swcpup_sqe commands are recognized with the second edge of the wr or rd_ pulses. *25 in cases when the busy bit of the cntl register is set to "0," cpu interrupt with the swcpup, swcpup_im, and swcpup_sqe commands are executed from the second edge of the wr or rd_ pulses. the swcpup and swcpup_sqe commands are executed in the last cycle of the ip/op sequence. the swcpup_im command is executed in a cycle when the interrupt is recognized. *26 in cases when the busy bit of the cntl register is set to "1," cpu interrupt with the swcpup, swcpup_im, and swcpup_sqe commands are recognized with the first edge of the wr or rd_ pulses. *27 in cases when the busy bit of the cntl register is set to "1," cpu interrupt with the swcpup, swcpup_im, and swcpup_sqe commands are executed from the first edge of the wr or rd_ pulses. the swcpup and swcpup_sqe commands are executed in the last cycle of the ip/op sequence. the swcpup_im command is executed in a cycle when the interrupt is recognized. *28 in the case of the hardware channel selection. *29 in the case of the software channel selection. *30 the sh0_ and sh1_ pins are initialized to a high impedance state by the sequence pointer reset. the transition time to a high impedance state is measured when a 400mv change from the loaded v oh /v ol level occurs. no. parameter min. max. unit note cpu interrupt 71 cpu interrupt to wr inactive 15 ns * 24 72 wr inactive to ipbusy_/opact_ transition time 30 ns * 25 73 cpu interrupt to wr active 15 ns * 26 74 wr active to ipbusy_/opact_ transition time 30 ns * 27 75 cpu interrupt to rd_ high 15 ns * 24 76 rd_ high to opbusy_/ipact_ transition time 30 ns * 25 77 cpu interrupt to rd_ low 15 ns * 26 78 rd_ low to opbusy_/ipact_ transition time 30 ns * 27 device reset and sequence pointer reset 79 rst_ width low 40 ns 80 sqrst_ width low 40 ns 81 ipch, opch setup time to sqrst_ 5 ns * 28 or ce_(ssqrst command) low 82 ipch, opch hold time after sqrst_ 15 ns * 28 or ce_(ssqrst command) low 83 insm<2:0> setup time to sqrst_ 5 ns * 29 or ce_(ssqrst command) low 84 insm<2:0> hold time after sqrst_ 15 ns * 29 or ce_(ssqrst command) low 85 opns setup time to sqrst_ 5 ns or ce_(ssqrst command) low 86 opns hold time after sqrst_ 15 ns or ce_(ssqrst command) low 87 ce_(ssqrst command) high to sh0, sh1 40 ns * 30 transition time
14-7 address processor ke5b256b1 *31 in the case of the ip sequence with the hha automatic output. note : characteristics are measured under the following conditions. input "h" level 2.8 v input "l" level 0.0 v input reference voltage 1.4v input signal through rate 1.0 ns/v output judgment level v dd /2 logical capacitance(c l ) 50 pf "h" level output loading current (i oh ) -4 ma "l" level output loading current (i ol )4 ma test loads no. parameter min. max. unit note s ig nal propagation in the cas caded s ys tem 88 hi_, pi_ to ho_, po_ trans ition time 20 ns 89 fli_ to flo_ trans ition time 20 ns hha automatic output 90 wr to od<31:0> trans ition time 115 ns * 31 dut c l i oh i ol v dd /2
14-8 address processor ke5b256b1 input port cycle wr id<31:0> ho_ po_ sh0_, sh1_ wr 1 2 3 4 8 9 5 6 valid valid valid 7 10
14-9 address processor ke5b256b1 output port cycle rd_ od<31:0> pi_, hi_ po_ ho_ rd_ oe_ od<31:0> valid valid valid valid 11 12 13 14 15 16 17 18 19 20 21 22 23
14-10 address processor ke5b256b1 cpu port write cycle ce_ hi_, pi_,fli_ dat<15:0> po_ ho_ ce_ valid valid add<7:0> r/w_ flo_ valid 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
14-11 address processor ke5b256b1 cpu port read cycle valid ce_ hi_, pi_, fli_ dat<15:0> po_ ho_ ce_ valid valid add<7:0> r/w_ flo_ valid 24 25 26 27 28 31 32 33 34 42 41 43 35 36 37 38 39 40
14-12 address processor ke5b256b1 pulse to pulse rd_ wr ce_ wr wr rd_ ce_ rd_ wr ce_ rd_ ce_ 45 44 47 46 49 48 51 50 52 53 54 55
14-13 address processor ke5b256b1 pulse to pulse (cont'd) ce_ rst_ wr sqrst_ ce_ (ssqrst command) sqrst_ ce_ (ssqrst command) rd_ sqrst_ ce_ (ssqrst command) wr sqrst_ ce_ (ssqrst command) rd_ 56 57 58 59 60 61 62
14-14 address processor ke5b256b1 ipbusy_/opact, opbusy_/ipact_ transition from ce_ ipbusy_/opact_ ce_ opbusy_/ipact_ ipbusy_/opact_ ce_ opbusy_/ipact_ ipbusy_/opact_ ce_ opbusy_/ipact_ ipbusy_/opact_ ce_ opbusy_/ipact_ (a) srst command (b) swiop command (sp/tp_ pull down) (d) swcpup and cwcpup_im commands in the iop mode (sp/tp_ pull down) (c) automatic swiop (sp/tp_ pull down) iop mode cpu mode cpu mode iop mode iop mode cpu mode (sp/tp_ pull down) 63 63 64 63 cpu mode
14-15 address processor ke5b256b1 opbusy_/ipact_ transition from wr wr opbusy_/ipact_ ip sequence start (busy bit ="0"/"1") ip mode iop mode ip mode iop mode wr opbusy_/ipact_ wr opbusy_/ipact_ (a) ip sequence end (busy bit ="0") (b) ip sequence end (busy bit ="1") iop mode ip mode (sp/tp_ pull down) (sp/tp_ pull down) (sp/tp_ pull down) 65 66 65
14-16 address processor ke5b256b1 ipbusy_/opact_ transition from rd_ rd_ ipbusy_/opact_ op mode iop mode op mode iop mode rd_ ipbusy_/opact_ rd_ ipbusy_/opact_ (a) op sequence start (busy bit = "0"/"1") (b) op sequence end (busy bit ="0") op sequence end (busy bit ="1") iop mode op mode (sp/tp_ pull down) (sp/tp_ pull down) (sp/tp_ pull down) 68 67 67
14-17 address processor ke5b256b1 sequence pointer reset operation in the middle of the sequence sqrst_ opbusy_/ipact_ (a) sequence pointer reset operation in the middle of the ip sequence iop mode ip mode ce_ (ssqrst command) sqrst_ ipbusy_/opact_ iop mode op mode ce_ (ssqrst command) (sp/tp_ pull down) (b) sequence pointer reset operation in the middle of the op sequence (sp/tp_ pull down) 69 70
14-18 address processor ke5b256b1 (a) busy bit ="0" (b) busy bit ="1" cpu interrupt in the middle of the ip sequence (sp/tp_ pull down) wr ipbusy_/opact_ cpu mode ip mode ce_ (cpu interrupt command) accepts interrupt executes interrupt ipbusy_/opact_ cpu mode wr accepts interrupt executes interrupt ce_ (cpu interrupt command) 71 72 73 74 ip mode
14-19 address processor ke5b256b1 (a) busy bit = "0" (b) busy bit = "1" cpu interrupt in the middle of the op sequence (sp/tp_ pull down) opbusy_/ipact_ cpu mode op mode ce_ (cpu interrupt command) accepts interrupt executes interrupt rd_ opbusy_/ipact_ cpu mode op mode rd_ ce_ (cpu interrupt command) accepts interrupt executes interrupt 75 76 77 78
14-20 address processor ke5b256b1 device reset and sequence pointer reset operation rst_ sh0_, sh1_ sqrst_ sqrst_ ipch, opch isnm<2:0> ce_ (ssqrst command) sqrst_ ce_ (ssqrst command) opns (a) hardware reset (b) selection channel and start sequence number (c) initializes sh0_, sh1_ pins 79 80 81 82 83 84 85 86 87
14-21 address processor ke5b256b1 hi_, pi_ delay in a cascaded system ho_, po_ fli_ flo_ hha automatic output wr od<31:0> valid 88 89 90 91
15-1 address processor ke5b256b1 unit:mm 15. package outline 108 73 109 144 136 37 72 31.2 0.4 28.0 0.1 28.0 0.1 31.2 0.4 0o ~ 12o 0.15 0.05 3.35typ 3.85max 1.6typ 0.8typ 0.65typ 0.3 0.1 index
? for more information or questions about kawasaki lsi cam products contact: kawasaki lsi u. s. a. inc. 2570 north first street, suite # 301, 501 edgewater dr., suite 510 san jose, ca 95131 wakefield, ma 01880 phone 408-570-0555 phone 617-224-4201 fax 408-570-0567 fax 617-224-2503 internet info@klsi.com or kawasaki steel corp. makuhari techno garden b5 1-3 nakase mihama-ku, chiba 261-01, japan phone 81-43-296-7432 fax 81-43-296-7419 internet klsi@lsidiv.kawasaki-steel.co.jp kawasaki lsi reserves the right to make changes without further notice to any products herein to improve reliab ility, function or design. kawasaki lsi does not assume any liability arising out of the application or use of any p roducts or circuit described herein ; neither does it convey any license under its patent rights nor the rights of oth ers. kawasaki lsi products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other a pplication in which the failure of the kawasaki lsi products could create a situation where personal injury or death may occur. should buyer purchase or use kawasaki lsi products for any such unintended or unauthorized application, buyer shall indemnify and hold kawasaki lsi and its officers, employees subsidiaries, affiliates, and distributors harml ess against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indi rectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that kawasaki lsi was negligent regarding the design or manufacture of the part.

▲Up To Search▲

Price & Availability of KE5B256B1CFP

	To Download KE5B256B1CFP Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .